Henry Stracovsky

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Training and operations with a double buffered memory topology
- Patent number 12,141,081
- Issue date Nov 12, 2024
- RAMBUS INC.
- Chi-Ming Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system design using buffer(s) on a mother board
- Patent number 11,907,139
- Issue date Feb 20, 2024
- RAMBUS INC.
- Chi-Ming Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Training and operations with a double buffered memory topology
- Patent number 11,768,780
- Issue date Sep 26, 2023
- RAMBUS INC.
- Chi-Ming Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system design using buffer(s) on a mother board
- Patent number 11,537,540
- Issue date Dec 27, 2022
- RAMBUS INC.
- Chi-Ming Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Training and operations with a double buffered memory topology
- Patent number 11,294,830
- Issue date Apr 5, 2022
- RAMBUS INC.
- Chi-Ming Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system design using buffer(s) on a mother board
- Patent number 11,003,601
- Issue date May 11, 2021
- Rambus, Inc.
- Chi-Ming Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system design using buffer(S) on a mother board
- Patent number 10,614,002
- Issue date Apr 7, 2020
- Rambus Inc.
- Chi-Ming Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Training and operations with a double buffered memory topology
- Patent number 10,613,995
- Issue date Apr 7, 2020
- Rambus Inc.
- Chi-Ming Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system design using buffer(s) on a mother board
- Patent number 10,169,258
- Issue date Jan 1, 2019
- Rambus Inc.
- Chi-Ming Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error detection and correction apparatus and method
- Patent number 9,043,674
- Issue date May 26, 2015
- Intel Corporation
- Wei Wu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reliability support in memory systems without error correcting code...
- Patent number 8,495,464
- Issue date Jul 23, 2013
- Intel Corporation
- Henry Stracovsky
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD
- Publication number 20240220428
- Publication date Jul 4, 2024
- Rambus Inc.
- Chi-Ming YEUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY
- Publication number 20240045813
- Publication date Feb 8, 2024
- Rambus Inc.
- Chi-Ming YEUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD
- Publication number 20230236997
- Publication date Jul 27, 2023
- Rambus Inc.
- Chi-Ming YEUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY
- Publication number 20220334981
- Publication date Oct 20, 2022
- Rambus Inc.
- Chi-Ming YEUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD
- Publication number 20210326279
- Publication date Oct 21, 2021
- Rambus Inc.
- Chi-Ming YEUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD
- Publication number 20200293468
- Publication date Sep 17, 2020
- RAMBUS INC.
- Chi-Ming YEUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY
- Publication number 20200293461
- Publication date Sep 17, 2020
- RAMBUS INC.
- Chi-Ming YEUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD
- Publication number 20190251044
- Publication date Aug 15, 2019
- RAMBUS INC.
- Chi-Ming YEUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD
- Publication number 20160364347
- Publication date Dec 15, 2016
- RAMBUS INC.
- Chi-Ming YEUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY
- Publication number 20160314822
- Publication date Oct 27, 2016
- RAMBUS INC.
- Chi-Ming YEUNG
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR DETECTION AND CORRECTION APPARATUS AND METHOD
- Publication number 20140181618
- Publication date Jun 26, 2014
- Wei Wu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RELIABILITY ENHANCEMENTS FOR HIGH SPEED MEMORY - PARITY PROTECTION...
- Publication number 20140089755
- Publication date Mar 27, 2014
- Shveta KANTAMSETTI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RELIABILITY SUPPORT IN MEMORY SYSTEMS WITHOUT ERROR CORRECTING CODE...
- Publication number 20110320913
- Publication date Dec 29, 2011
- Henry Stracovsky
- G06 - COMPUTING CALCULATING COUNTING

Henry Stracovsky

Person

Patents Grantslast 30 patents

Training and operations with a double buffered memory topology

Memory system design using buffer(s) on a mother board

Training and operations with a double buffered memory topology

Memory system design using buffer(s) on a mother board

Training and operations with a double buffered memory topology

Memory system design using buffer(s) on a mother board

Memory system design using buffer(S) on a mother board

Training and operations with a double buffered memory topology

Memory system design using buffer(s) on a mother board

Error detection and correction apparatus and method

Reliability support in memory systems without error correcting code...

Patents Applicationslast 30 patents

MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD

TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY

MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD

TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY

MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD

MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD

TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY

MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD

MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD

TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY

ERROR DETECTION AND CORRECTION APPARATUS AND METHOD

RELIABILITY ENHANCEMENTS FOR HIGH SPEED MEMORY - PARITY PROTECTION...

RELIABILITY SUPPORT IN MEMORY SYSTEMS WITHOUT ERROR CORRECTING CODE...