Herbert H. Hum

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
High performance interconnect
- Patent number 11,741,030
- Issue date Aug 29, 2023
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and method implementing a cacheline demote machine instru...
- Patent number 11,513,957
- Issue date Nov 29, 2022
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 11,366,511
- Issue date Jun 21, 2022
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 11,269,793
- Issue date Mar 8, 2022
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 11,054,890
- Issue date Jul 6, 2021
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware/software co-optimization to improve performance and energy...
- Patent number 10,817,425
- Issue date Oct 27, 2020
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processors having virtually clustered cores and cache slices
- Patent number 10,725,920
- Issue date Jul 28, 2020
- Intel Corporation
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processors having virtually clustered cores and cache slices
- Patent number 10,725,919
- Issue date Jul 28, 2020
- Intel Corporation
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processors having virtually clustered cores and cache slices
- Patent number 10,705,960
- Issue date Jul 7, 2020
- Intel Corporation
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 10,437,320
- Issue date Oct 8, 2019
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 10,409,360
- Issue date Sep 10, 2019
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 10,386,915
- Issue date Aug 20, 2019
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 10,248,591
- Issue date Apr 2, 2019
- Intel Corporation
- Robert J. Safranek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Efficient data transfer between a processor core and an accelerator
- Patent number 10,248,568
- Issue date Apr 2, 2019
- Intel Corporation
- Pinkesh Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processors having virtually clustered cores and cache slices
- Patent number 10,073,779
- Issue date Sep 11, 2018
- Intel Corporation
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for migrating processes among asymmetrical proc...
- Patent number 9,939,882
- Issue date Apr 10, 2018
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,910,483
- Issue date Mar 6, 2018
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient data transfer between a processor core and an accelerator
- Patent number 9,880,935
- Issue date Jan 30, 2018
- Intel Corporation
- Pinkesh Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,874,926
- Issue date Jan 23, 2018
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,870,046
- Issue date Jan 16, 2018
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,829,965
- Issue date Nov 28, 2017
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,760,162
- Issue date Sep 12, 2017
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of tasks among asymmetric processing elements
- Patent number 9,753,530
- Issue date Sep 5, 2017
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for efficient load processing using buffers
- Patent number 9,710,391
- Issue date Jul 18, 2017
- Intel Corporation
- Wei Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 9,626,321
- Issue date Apr 18, 2017
- Intel Corporation
- Robert J. Safranek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Cache coherency apparatus and method minimizing memory writeback op...
- Patent number 9,436,605
- Issue date Sep 6, 2016
- Intel Corporation
- Jeffrey D. Chamberlain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler assisted low power and high performance load handling base...
- Patent number 9,311,085
- Issue date Apr 12, 2016
- Intel Corporation
- Tingting Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Directory cache supporting non-atomic input/output operations
- Patent number 9,170,946
- Issue date Oct 27, 2015
- Intel Corporation
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for partial memory mirroring
- Patent number 9,037,903
- Issue date May 19, 2015
- Intel Corporation
- Herbert H Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaving data packets in a packet-based communication system
- Patent number 8,885,673
- Issue date Nov 11, 2014
- Intel Corporation
- Aaron T. Spink
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20240012772
- Publication date Jan 11, 2024
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20220114122
- Publication date Apr 14, 2022
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20210117350
- Publication date Apr 22, 2021
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS
- Publication number 20210089113
- Publication date Mar 25, 2021
- Intel Corporation
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20200356502
- Publication date Nov 12, 2020
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20190391939
- Publication date Dec 26, 2019
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DATA TRANSFER BETWEEN A PROCESSOR CORE AND AN ACCELERATOR
- Publication number 20190188136
- Publication date Jun 20, 2019
- Intel Corporation
- Pinkesh Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
- Publication number 20180225212
- Publication date Aug 9, 2018
- Intel Corporation
- Herbert H. HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
- Publication number 20180225213
- Publication date Aug 9, 2018
- Intel Corporation
- Herbert H. HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
- Publication number 20180225211
- Publication date Aug 9, 2018
- Intel Corporation
- Herbert H. HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DATA TRANSFER BETWEEN A PROCESSOR CORE AND AN ACCELERATOR
- Publication number 20180165193
- Publication date Jun 14, 2018
- Intel Corporation
- Pinkesh Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL
- Publication number 20170109286
- Publication date Apr 20, 2017
- Intel Corporation
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20170109315
- Publication date Apr 20, 2017
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distribution of Tasks Among Asymmetric Processing Elements
- Publication number 20170024001
- Publication date Jan 26, 2017
- HERBERT HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distribution of Tasks Among Asymmetric Processing Elements
- Publication number 20160370852
- Publication date Dec 22, 2016
- HERBERT HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distribution of Tasks Among Asymmetric Processing Elements
- Publication number 20160370851
- Publication date Dec 22, 2016
- HERBERT HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY...
- Publication number 20160188474
- Publication date Jun 30, 2016
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DATA TRANSFER BETWEEN A PROCESSOR CORE AND AN ACCELERATOR
- Publication number 20150269074
- Publication date Sep 24, 2015
- Pinkesh Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCY APPARATUS AND METHOD MINIMIZING MEMORY WRITEBACK OP...
- Publication number 20150178206
- Publication date Jun 25, 2015
- Jeffrey D. Chamberlain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID INPUT/OUTPUT WRITE OPERATIONS
- Publication number 20150113221
- Publication date Apr 23, 2015
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL
- Publication number 20150081984
- Publication date Mar 19, 2015
- Intel Corporation
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS
- Publication number 20150012766
- Publication date Jan 8, 2015
- Herbert HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS
- Publication number 20150012765
- Publication date Jan 8, 2015
- Herbert HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS
- Publication number 20150012731
- Publication date Jan 8, 2015
- Herbert HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL
- Publication number 20140201463
- Publication date Jul 17, 2014
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
- Publication number 20140189239
- Publication date Jul 3, 2014
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR PARTIAL MEMORY MIRRORING
- Publication number 20140189417
- Publication date Jul 3, 2014
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS
- Publication number 20140181394
- Publication date Jun 26, 2014
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS
- Publication number 20140130058
- Publication date May 8, 2014
- Herbert Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20140112339
- Publication date Apr 24, 2014
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING

Herbert H. Hum

Person

Patents Grantslast 30 patents

High performance interconnect

Processor and method implementing a cacheline demote machine instru...

Distribution of tasks among asymmetric processing elements

High performance interconnect

Distribution of tasks among asymmetric processing elements

Hardware/software co-optimization to improve performance and energy...

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

High performance interconnect

Efficient data transfer between a processor core and an accelerator

Processors having virtually clustered cores and cache slices

Systems and methods for migrating processes among asymmetrical proc...

Distribution of tasks among asymmetric processing elements

Efficient data transfer between a processor core and an accelerator

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Distribution of tasks among asymmetric processing elements

Methods and apparatuses for efficient load processing using buffers

High performance interconnect

Cache coherency apparatus and method minimizing memory writeback op...

Compiler assisted low power and high performance load handling base...

Directory cache supporting non-atomic input/output operations

Apparatus and method for partial memory mirroring

Interleaving data packets in a packet-based communication system

Patents Applicationslast 30 patents

HIGH PERFORMANCE INTERCONNECT

HIGH PERFORMANCE INTERCONNECT

HIGH PERFORMANCE INTERCONNECT

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

HIGH PERFORMANCE INTERCONNECT

HIGH PERFORMANCE INTERCONNECT

EFFICIENT DATA TRANSFER BETWEEN A PROCESSOR CORE AND AN ACCELERATOR

PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES

PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES

PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES

EFFICIENT DATA TRANSFER BETWEEN A PROCESSOR CORE AND AN ACCELERATOR

HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL

HIGH PERFORMANCE INTERCONNECT

Distribution of Tasks Among Asymmetric Processing Elements

Distribution of Tasks Among Asymmetric Processing Elements

Distribution of Tasks Among Asymmetric Processing Elements

HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY...

EFFICIENT DATA TRANSFER BETWEEN A PROCESSOR CORE AND AN ACCELERATOR

CACHE COHERENCY APPARATUS AND METHOD MINIMIZING MEMORY WRITEBACK OP...

HYBRID INPUT/OUTPUT WRITE OPERATIONS

HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL

PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES

APPARATUS AND METHOD FOR PARTIAL MEMORY MIRRORING

DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

HIGH PERFORMANCE INTERCONNECT