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Herbert Johannes Preuthen
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Dorfen, DE
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Patents Grants
last 30 patents
Information
Patent Grant
Edge cell signal line antenna diodes
Patent number
11,450,753
Issue date
Sep 20, 2022
GLOBALFOUNDRIES U.S. INC.
Stefan Block
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Transistor cell for integrated circuits and method to form same
Patent number
11,329,129
Issue date
May 10, 2022
GLOBALFOUNDRIES U.S. INC.
Stefan G. Block
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Simplified bias scheme for digital designs
Patent number
10,505,545
Issue date
Dec 10, 2019
GLOBALFOUNDRIES Inc.
Stefan Block
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Placing and routing method for implementing back bias in FDSOI
Patent number
10,114,919
Issue date
Oct 30, 2018
GLOBALFOUNDRIES Inc.
Herbert Johannes Preuthen
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Timing violation debugging inside place and route tool
Patent number
8,584,068
Issue date
Nov 12, 2013
LSI Corporation
Matthias Dinter
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Clock tree insertion delay independent interface
Patent number
8,564,337
Issue date
Oct 22, 2013
LSI Corporation
Stefan Block
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Test pin gating for dynamic optimization
Patent number
8,078,926
Issue date
Dec 13, 2011
LSI Corporation
Stefan G. Block
G01 - MEASURING TESTING
Information
Patent Grant
Timing violation debugging inside place and route tool
Patent number
7,747,975
Issue date
Jun 29, 2010
LSI Corporation
Matthias Dinter
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Config logic power saving method
Patent number
7,616,517
Issue date
Nov 10, 2009
LSI Corporation
Stephan Habel
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Advanced standard cell power connection
Patent number
7,398,489
Issue date
Jul 8, 2008
LSI Corporation
Matthias Dinter
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Automatic placement based ESD protection insertion
Patent number
7,334,207
Issue date
Feb 19, 2008
LSI Logic Corporation
Herbert Johannes Preuthen
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Engineering change order scenario manager
Patent number
7,331,028
Issue date
Feb 12, 2008
LSI Logic Corporation
Matthias Dinter
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Timing violation debugging inside place and route tool
Patent number
7,325,215
Issue date
Jan 29, 2008
LSI Logic Corporation
Matthias Dinter
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
TRANSISTOR CELL FOR INTEGRATED CIRCUITS AND METHOD TO FORM SAME
Publication number
20210159313
Publication date
May 27, 2021
GLOBALFOUNDRIES U.S. Inc.
Stefan G. Block
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
EDGE CELL SIGNAL LINE ANTENNA DIODES
Publication number
20200357897
Publication date
Nov 12, 2020
GLOBALFOUNDRIES INC.
Stefan Block
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
PLACING AND ROUTING METHOD FOR IMPLEMENTING BACK BIAS IN FDSOI
Publication number
20170235865
Publication date
Aug 17, 2017
GLOBALFOUNDRIES INC.
Herbert Johannes Preuthen
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
MEMORY CELL, MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELLS AN...
Publication number
20160284392
Publication date
Sep 29, 2016
GLOBALFOUNDRIES INC.
Stefan Block
G11 - INFORMATION STORAGE
Information
Patent Application
CLOCK TREE INSERTION DELAY INDEPENDENT INTERFACE
Publication number
20120200322
Publication date
Aug 9, 2012
LSI Corporation
Stefan Block
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Delay-Cell Footprint-Compatible Buffers
Publication number
20110320997
Publication date
Dec 29, 2011
LSI Corporation
Farid Labib
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Test Pin Gating for Dynamic Optimization
Publication number
20110066905
Publication date
Mar 17, 2011
LSI Corporation
Stefan G. Block
G01 - MEASURING TESTING
Information
Patent Application
TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL
Publication number
20100229141
Publication date
Sep 9, 2010
Matthias Dinter
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL
Publication number
20080077903
Publication date
Mar 27, 2008
Matthias Dinter
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Timing violation debugging inside place and route tool
Publication number
20070050745
Publication date
Mar 1, 2007
LSI Logic Corporation
Matthias Dinter
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Automatic placement based ESD protection insertion
Publication number
20060268486
Publication date
Nov 30, 2006
LSI Logic Corporation
Herbert Johannes Preuthen
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
Advanced standard cell power connection
Publication number
20060226530
Publication date
Oct 12, 2006
LSI Logic Corporation
Matthias Dinter
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Engineering change order scenario manager
Publication number
20060026546
Publication date
Feb 2, 2006
Matthias Dinter
G06 - COMPUTING CALCULATING COUNTING