Herman Henry Schmit

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sharding for synchronous processors
- Patent number 12,147,793
- Issue date Nov 19, 2024
- Google LLC
- Reiner Pope
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for reducing uneven aging in integrated circuits
- Patent number 11,799,485
- Issue date Oct 24, 2023
- Intel Corporation
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed programmable delay lines in a clock tree
- Patent number 11,210,443
- Issue date Dec 28, 2021
- Intel Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for reducing uneven aging in integrated circuits
- Patent number 11,159,167
- Issue date Oct 26, 2021
- Intel Corporation
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for routing data across regions of an integrate...
- Patent number 11,115,026
- Issue date Sep 7, 2021
- Intel Corporation
- Sean R. Atsatt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for implementing learned parameter systems on a...
- Patent number 10,860,760
- Issue date Dec 8, 2020
- Intel Corporation
- Thiam Khean Hah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a system-level design tool fo...
- Patent number 10,678,979
- Issue date Jun 9, 2020
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for routing data across regions of an integrate...
- Patent number 10,587,273
- Issue date Mar 10, 2020
- Intel Corporation
- Sean R. Atsatt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable circuit having multiple sectors
- Patent number 10,523,207
- Issue date Dec 31, 2019
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Network-on-chip with fixed and configurable functions
- Patent number 10,367,745
- Issue date Jul 30, 2019
- Altera Corporation
- Dana How
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable logic device with integrated network-on-chip
- Patent number 10,367,756
- Issue date Jul 30, 2019
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional design-dependent voltage control and clocking
- Patent number 10,303,834
- Issue date May 28, 2019
- Intel Corporation
- David Michael Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for embedding an error correction code in sto...
- Patent number 10,289,483
- Issue date May 14, 2019
- Altera Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lutram dummy read scheme during error detection and correction
- Patent number 10,191,661
- Issue date Jan 29, 2019
- Altera Corporation
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for routing data across regions of an integrate...
- Patent number 10,187,064
- Issue date Jan 22, 2019
- Intel Corporation
- Sean R. Atsatt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pipelined interconnect circuitry with double data rate interconnect...
- Patent number 10,141,936
- Issue date Nov 27, 2018
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for a low hold-time sequential input stage
- Patent number 10,044,344
- Issue date Aug 7, 2018
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit design implementations in secure partitions of an integrate...
- Patent number 9,946,826
- Issue date Apr 17, 2018
- Altera Corporation
- Sean Atsatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sector-based clock routing methods and apparatus
- Patent number 9,922,157
- Issue date Mar 20, 2018
- Altera Corporation
- Carl Ebeling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry for implementing multi-mode redundancy and arithmetic fun...
- Patent number 9,813,061
- Issue date Nov 7, 2017
- Altera Corporation
- Herman Henry Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for a low hold-time sequential input stage
- Patent number 9,806,696
- Issue date Oct 31, 2017
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for operating configurable storage and processing blocks at...
- Patent number 9,768,783
- Issue date Sep 19, 2017
- Altera Corporation
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for handling high voltage circuitry in an integrated cir...
- Patent number 9,755,647
- Issue date Sep 5, 2017
- Altera Corporation
- Andy Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for implementing a system-level design tool fo...
- Patent number 9,740,808
- Issue date Aug 22, 2017
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined interconnect circuitry with double data rate interconnect...
- Patent number 9,692,418
- Issue date Jun 27, 2017
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable clock grid structures
- Patent number 9,606,573
- Issue date Mar 28, 2017
- Altera Corporation
- Carl Ebeling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for detecting memory bit corruption on an int...
- Patent number 9,582,349
- Issue date Feb 28, 2017
- Altera Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network-on-chip with fixed and configurable functions
- Patent number 9,553,762
- Issue date Jan 24, 2017
- Altera Corporation
- Dana How
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for decomposing functions in a configurable IC
- Patent number 9,507,900
- Issue date Nov 29, 2016
- Altera Corporation
- Andrew Caldwell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for implementing a system-level design tool fo...
- Patent number 9,507,883
- Issue date Nov 29, 2016
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SHARDING FOR SYNCHRONOUS PROCESSORS
- Publication number 20250045032
- Publication date Feb 6, 2025
- Google LLC
- Reiner Pope
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semi-Constant Operand Multipliers
- Publication number 20250004717
- Publication date Jan 2, 2025
- Google LLC
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTO-CREATION OF CUSTOM STANDARD CELLS
- Publication number 20240176943
- Publication date May 30, 2024
- X Development LLC
- Xiaoqing Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSISTOR-LEVEL SYNTHESIS
- Publication number 20240169134
- Publication date May 23, 2024
- Alessandro Tempia Calvino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Input Serial Adder
- Publication number 20230367549
- Publication date Nov 16, 2023
- Google LLC
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARDING FOR SYNCHRONOUS PROCESSORS
- Publication number 20220300450
- Publication date Sep 22, 2022
- Google LLC
- Reiner Pope
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
- Publication number 20220224656
- Publication date Jul 14, 2022
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques For Reducing Uneven Aging In Integrated Circuits
- Publication number 20220014201
- Publication date Jan 13, 2022
- Intel Corporation
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR ROUTING DATA ACROSS REGIONS OF AN INTEGRATE...
- Publication number 20200153438
- Publication date May 14, 2020
- Intel Corporation
- Sean R. Atsatt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable Circuit Having Multiple Sectors
- Publication number 20200136624
- Publication date Apr 30, 2020
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NETWORK-ON-CHIP WITH FIXED AND CONFIGURABLE FUNCTIONS
- Publication number 20190327176
- Publication date Oct 24, 2019
- Altera Corporation
- Dana How
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
- Publication number 20190215280
- Publication date Jul 11, 2019
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED PROGRAMMABLE DELAY LINES IN A CLOCK TREE
- Publication number 20190179990
- Publication date Jun 13, 2019
- Intel Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR ROUTING DATA ACROSS REGIONS OF AN INTEGRATE...
- Publication number 20190165789
- Publication date May 30, 2019
- Intel Corporation
- Sean R. Atsatt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Techniques For Reducing Uneven Aging In Integrated Circuits
- Publication number 20190097635
- Publication date Mar 28, 2019
- Intel Corporation
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGIONAL DESIGN-DEPENDENT VOLTAGE CONTROL AND CLOCKING
- Publication number 20180373831
- Publication date Dec 27, 2018
- Intel Corporation
- David Michael Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPLEMENTING LEARNED PARAMETER SYSTEMS ON A...
- Publication number 20180307783
- Publication date Oct 25, 2018
- Intel Corporation
- Thiam Khean Hah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques For Handling High Voltage Circuitry In An Integrated Cir...
- Publication number 20180109262
- Publication date Apr 19, 2018
- Altera Corporation
- Andy Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR A LOW HOLD-TIME SEQUENTIAL INPUT STAGE
- Publication number 20180069533
- Publication date Mar 8, 2018
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and Apparatus for Implementing a System-Level Design Tool fo...
- Publication number 20170316120
- Publication date Nov 2, 2017
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED INTERCONNECT CIRCUITRY WITH DOUBLE DATA RATE INTERCONNECT...
- Publication number 20170288671
- Publication date Oct 5, 2017
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and Apparatus for Implementing a System-Level Design Tool fo...
- Publication number 20170046455
- Publication date Feb 16, 2017
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Logic Device With Integrated Network-On-Chip
- Publication number 20170041249
- Publication date Feb 9, 2017
- Altera Corporation
- Michael David Hutton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN STO...
- Publication number 20160378599
- Publication date Dec 29, 2016
- Altera Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN MEM...
- Publication number 20160294413
- Publication date Oct 6, 2016
- Altera Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Operational Time Extension
- Publication number 20160087635
- Publication date Mar 24, 2016
- Altera Corporation
- Andre Rohe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE CIRCUIT HAVING MULTIPLE SECTORS
- Publication number 20160049941
- Publication date Feb 18, 2016
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC
- Publication number 20160028399
- Publication date Jan 28, 2016
- Altera Corporation
- Brad Hutchings
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHODS FOR DETERMINING LATENCY OF A NETWORK PORT
- Publication number 20150281031
- Publication date Oct 1, 2015
- Altera Corporation
- Herman SCHMIT
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Configurable IC's With Large Carry Chains
- Publication number 20150137851
- Publication date May 21, 2015
- Tabula, Inc.
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING

Herman Henry Schmit

Person

Patents Grantslast 30 patents

Sharding for synchronous processors

Techniques for reducing uneven aging in integrated circuits

Distributed programmable delay lines in a clock tree

Techniques for reducing uneven aging in integrated circuits

Systems and methods for routing data across regions of an integrate...

Systems and methods for implementing learned parameter systems on a...

Method and apparatus for implementing a system-level design tool fo...

Systems and methods for routing data across regions of an integrate...

Programmable circuit having multiple sectors

Network-on-chip with fixed and configurable functions

Programmable logic device with integrated network-on-chip

Regional design-dependent voltage control and clocking

Methods and apparatus for embedding an error correction code in sto...

Lutram dummy read scheme during error detection and correction

Systems and methods for routing data across regions of an integrate...

Pipelined interconnect circuitry with double data rate interconnect...

Systems and methods for a low hold-time sequential input stage

Circuit design implementations in secure partitions of an integrate...

Sector-based clock routing methods and apparatus

Circuitry for implementing multi-mode redundancy and arithmetic fun...

Systems and methods for a low hold-time sequential input stage

Methods for operating configurable storage and processing blocks at...

Techniques for handling high voltage circuitry in an integrated cir...

Method and apparatus for implementing a system-level design tool fo...

Pipelined interconnect circuitry with double data rate interconnect...

Configurable clock grid structures

Methods and apparatus for detecting memory bit corruption on an int...

Network-on-chip with fixed and configurable functions

Method and apparatus for decomposing functions in a configurable IC

Method and apparatus for implementing a system-level design tool fo...

Patents Applicationslast 30 patents

SHARDING FOR SYNCHRONOUS PROCESSORS

Semi-Constant Operand Multipliers

AUTO-CREATION OF CUSTOM STANDARD CELLS

TRANSISTOR-LEVEL SYNTHESIS

Multiple Input Serial Adder

SHARDING FOR SYNCHRONOUS PROCESSORS

PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP

Techniques For Reducing Uneven Aging In Integrated Circuits

SYSTEMS AND METHODS FOR ROUTING DATA ACROSS REGIONS OF AN INTEGRATE...

Programmable Circuit Having Multiple Sectors

NETWORK-ON-CHIP WITH FIXED AND CONFIGURABLE FUNCTIONS

PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP

DISTRIBUTED PROGRAMMABLE DELAY LINES IN A CLOCK TREE

SYSTEMS AND METHODS FOR ROUTING DATA ACROSS REGIONS OF AN INTEGRATE...

Techniques For Reducing Uneven Aging In Integrated Circuits

REGIONAL DESIGN-DEPENDENT VOLTAGE CONTROL AND CLOCKING

SYSTEMS AND METHODS FOR IMPLEMENTING LEARNED PARAMETER SYSTEMS ON A...

Techniques For Handling High Voltage Circuitry In An Integrated Cir...

SYSTEMS AND METHODS FOR A LOW HOLD-TIME SEQUENTIAL INPUT STAGE

Method and Apparatus for Implementing a System-Level Design Tool fo...

PIPELINED INTERCONNECT CIRCUITRY WITH DOUBLE DATA RATE INTERCONNECT...

Method and Apparatus for Implementing a System-Level Design Tool fo...

Programmable Logic Device With Integrated Network-On-Chip

METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN STO...

METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN MEM...

Operational Time Extension

PROGRAMMABLE CIRCUIT HAVING MULTIPLE SECTORS

RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC

APPARATUS AND METHODS FOR DETERMINING LATENCY OF A NETWORK PORT

Configurable IC's With Large Carry Chains