Herve G. Duprez

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Campbell, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Method for verifying circuit layout design
- Patent number 5,450,331
- Issue date Sep 12, 1995
- VLSI Technology, Inc.
- Pei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for labelling polygons
- Patent number 5,113,451
- Issue date May 12, 1992
- VLSI Technology, Inc.
- David C. Chapman
- G06 - COMPUTING CALCULATING COUNTING