Hidefumi Yamamoto

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Takatsuki-city, JP

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Patents Grantslast 30 patents

Information Patent Grant
Method for packaging electronic devices and integrated circuits
- Patent number 8,399,293
- Issue date Mar 19, 2013
- Wafer-Level Packaging Portfolio LLC
- Juergen Leib
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method for packaging electronic devices and integrated circuits
- Patent number 8,017,435
- Issue date Sep 13, 2011
- Wafer-Level Packaging Portfolio LLC
- Juergen Leib
- B81 - MICRO-STRUCTURAL TECHNOLOGY

Patents Applicationslast 30 patents

Information Patent Application
Method for Packaging Electronic Devices and Integrated Circuits
- Publication number 20120003791
- Publication date Jan 5, 2012
- WAFER-LEVEL PACKAGING PORTFOLIO LLC
- Juergen Leib
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Method for packaging electronic devices and integrated circuits
- Publication number 20100059877
- Publication date Mar 11, 2010
- SCHOTT AG
- Juergen Leib
- B81 - MICRO-STRUCTURAL TECHNOLOGY