Hideki ARAKAWA

Person

Yokahama, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Voltage generating circuit and regulator circuit for precisely cont...
- Patent number 9,537,398
- Issue date Jan 3, 2017
- Powerchip Technology Corporation
- Hideki Arakawa
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Negative reference voltage generating circuit
- Patent number 9,502,969
- Issue date Nov 22, 2016
- Powerchip Technology Corporation
- Hideki Arakawa
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Negative reference voltage generating circuit and system thereof
- Patent number 9,397,562
- Issue date Jul 19, 2016
- Powerchip Technology Corporation
- Hideki Arakawa
- G05 - CONTROLLING REGULATING
Information Patent Grant
Transistor formation method using sidewall masks
- Patent number 9,299,578
- Issue date Mar 29, 2016
- Cypress Semiconductor Corporation
- Hideki Arakawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programming method for NAND flash memory device to reduce electrons...
- Patent number 9,214,242
- Issue date Dec 15, 2015
- Powerchip Corporation
- Takashi Miida
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile semiconductor storage device and control method thereof
- Patent number 9,076,546
- Issue date Jul 7, 2015
- Powerchip Technology Corp.
- Akitomo Nakayama
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming method for NAND flash memory device to reduce electrons...
- Patent number 8,599,614
- Issue date Dec 3, 2013
- Powerchip Corporation
- Takashi Miida
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and data reading method
- Patent number 8,131,954
- Issue date Mar 6, 2012
- Powerchip Technology Corporation
- Chun-Yi Tu
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuits and discharge circuits
- Patent number 7,903,470
- Issue date Mar 8, 2011
- Powerchip Semiconductor Corp.
- Te-Chang Tseng
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage device and control method thereof
- Patent number 7,881,142
- Issue date Feb 1, 2011
- Spansion LLC
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory programming method and data access method
- Patent number 7,778,087
- Issue date Aug 17, 2010
- Powerchip Semiconductor Corp.
- Chun-Yi Tu
- G11 - INFORMATION STORAGE
Information Patent Grant
SONOS memory with inversion bit-lines
- Patent number 7,501,677
- Issue date Mar 10, 2009
- Spansion LLC
- Hidehiko Shiraiwa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and method of controlling the same
- Patent number 7,385,844
- Issue date Jun 10, 2008
- Spansion LLC
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling a nonvolatile storage device
- Patent number 7,372,743
- Issue date May 13, 2008
- Spansion, LLC
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and method of controlling the same
- Patent number 7,362,620
- Issue date Apr 22, 2008
- Spansion LLC
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and method for controlling operation thereof
- Patent number 7,321,511
- Issue date Jan 22, 2008
- Spansion LLC
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage device and control method therefor
- Patent number 7,274,602
- Issue date Sep 25, 2007
- Spansion LLC
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
SONOS memory with inversion bit-lines
- Patent number 7,151,293
- Issue date Dec 19, 2006
- Spansion, LLC
- Hidehiko Shiraiwa
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller for multilevel cell memory
- Patent number 7,096,406
- Issue date Aug 22, 2006
- Spansion LLC
- Keisuke Kanazawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory device
- Patent number 6,385,088
- Issue date May 7, 2002
- Sony Corporation
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shift circuit with low voltage operation
- Patent number 6,208,200
- Issue date Mar 27, 2001
- Sony Corporation
- Hideki Arakawa
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Power supply circuit
- Patent number 5,883,501
- Issue date Mar 16, 1999
- Sony Corporation
- Hideki Arakawa
- G05 - CONTROLLING REGULATING
Information Patent Grant
Random access memory having flash memory
- Patent number 5,590,073
- Issue date Dec 31, 1996
- Sony Corporation
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage booster circuit
- Patent number 5,489,870
- Issue date Feb 6, 1996
- Sony Corporation
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile storage apparatus with folded bit line structure
- Patent number 5,459,694
- Issue date Oct 17, 1995
- Sony Corporation
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Single transistor flash electrically programmable memory cell in wh...
- Patent number 5,396,459
- Issue date Mar 7, 1995
- Sony Corporation
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having current to voltage conversion ty...
- Patent number 5,388,078
- Issue date Feb 7, 1995
- Sony Corporation
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically erasable and programmable read only memory using stack...
- Patent number 5,253,200
- Issue date Oct 12, 1993
- Sony Corporation
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Ultraviolet erasable nonvolatile memory with current mirror circuit...
- Patent number 5,198,997
- Issue date Mar 30, 1993
- Sony Corporation
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile random access memory device
- Patent number 5,189,641
- Issue date Feb 23, 1993
- Fujitsu Limited
- Hideki Arakawa
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
VOLTAGE GENERATING CIRCUIT, REGULATOR CIRCUIT, SEMICONDUCTOR STORAG...
- Publication number 20160233770
- Publication date Aug 11, 2016
- POWERCHIP TECHNOLOGY CORPORATION
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE REFERENCE VOLTAGE GENERATING CIRCUIT
- Publication number 20160211744
- Publication date Jul 21, 2016
- POWERCHIP TECHNOLOGY CORPORATION
- Hideki Arakawa
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
NEGATIVE REFERENCE VOLTAGE GENERATING CIRCUIT AND SYSTEM THEREOF
- Publication number 20160204699
- Publication date Jul 14, 2016
- POWERCHIP TECHNOLOGY CORPORATION
- Hideki Arakawa
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF
- Publication number 20150078100
- Publication date Mar 19, 2015
- POWERCHIP TECHNOLOGY CORPORATION
- Akitomo NAKAYAMA
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING METHOD FOR NAND FLASH MEMORY DEVICE TO REDUCE ELECTRONS...
- Publication number 20140140129
- Publication date May 22, 2014
- POWERCHIP TECHNOLOGY CORPORATION
- Takashi MIIDA
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING METHOD FOR NAND FLASH MEMORY DEVICE TO REDUCE ELECTRONS...
- Publication number 20110310666
- Publication date Dec 22, 2011
- Takashi Miida
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND DATA READING METHOD
- Publication number 20090177851
- Publication date Jul 9, 2009
- Chun-Yi TU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS AND DISCHARGE CIRCUITS
- Publication number 20090161440
- Publication date Jun 25, 2009
- Te-Chang TSENG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY PROGRAMMING METHOD AND DATA ACCESS METHOD
- Publication number 20090161426
- Publication date Jun 25, 2009
- Chun-Yi TU
- G11 - INFORMATION STORAGE
Information Patent Application
Controlling a nonvolatile storage device
- Publication number 20070183193
- Publication date Aug 9, 2007
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Application
Storage device and control method thereof
- Publication number 20070076492
- Publication date Apr 5, 2007
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Application
SONOS memory with inversion bit-lines
- Publication number 20070058442
- Publication date Mar 15, 2007
- Hidehiko Shiraiwa
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device and method of controlling the same
- Publication number 20070025154
- Publication date Feb 1, 2007
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Application
Storage device and control method therefor
- Publication number 20060280006
- Publication date Dec 14, 2006
- Hideki Arakawa
- G11 - INFORMATION STORAGE
Information Patent Application
Fabrication method for a semiconductor device
- Publication number 20060276032
- Publication date Dec 7, 2006
- Hideki Arakawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device and method for controlling operation thereof
- Publication number 20060256617
- Publication date Nov 16, 2006
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device and method of controlling the same
- Publication number 20060245247
- Publication date Nov 2, 2006
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Application
Memory controller for multilevel cell memory
- Publication number 20030041299
- Publication date Feb 27, 2003
- FUJITSU LIMITED
- Keisuke Kanazawa
- G06 - COMPUTING CALCULATING COUNTING

Hideki ARAKAWA

Person

Patents Grantslast 30 patents

Voltage generating circuit and regulator circuit for precisely cont...

Negative reference voltage generating circuit

Negative reference voltage generating circuit and system thereof

Transistor formation method using sidewall masks

Programming method for NAND flash memory device to reduce electrons...

Nonvolatile semiconductor storage device and control method thereof

Programming method for NAND flash memory device to reduce electrons...

Memory device and data reading method

Integrated circuits and discharge circuits

Storage device and control method thereof

Memory programming method and data access method

SONOS memory with inversion bit-lines

Semiconductor device and method of controlling the same

Controlling a nonvolatile storage device

Semiconductor device and method of controlling the same

Semiconductor device and method for controlling operation thereof

Storage device and control method therefor

SONOS memory with inversion bit-lines

Memory controller for multilevel cell memory

Non-volatile memory device

Level shift circuit with low voltage operation

Power supply circuit

Random access memory having flash memory

Voltage booster circuit

Nonvolatile storage apparatus with folded bit line structure

Single transistor flash electrically programmable memory cell in wh...

Semiconductor memory device having current to voltage conversion ty...

Electrically erasable and programmable read only memory using stack...

Ultraviolet erasable nonvolatile memory with current mirror circuit...

Non-volatile random access memory device

Patents Applicationslast 30 patents

VOLTAGE GENERATING CIRCUIT, REGULATOR CIRCUIT, SEMICONDUCTOR STORAG...

NEGATIVE REFERENCE VOLTAGE GENERATING CIRCUIT

NEGATIVE REFERENCE VOLTAGE GENERATING CIRCUIT AND SYSTEM THEREOF

NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF

PROGRAMMING METHOD FOR NAND FLASH MEMORY DEVICE TO REDUCE ELECTRONS...

PROGRAMMING METHOD FOR NAND FLASH MEMORY DEVICE TO REDUCE ELECTRONS...

MEMORY DEVICE AND DATA READING METHOD

INTEGRATED CIRCUITS AND DISCHARGE CIRCUITS

MEMORY PROGRAMMING METHOD AND DATA ACCESS METHOD

Controlling a nonvolatile storage device

Storage device and control method thereof

SONOS memory with inversion bit-lines

Semiconductor device and method of controlling the same

Storage device and control method therefor

Fabrication method for a semiconductor device

Semiconductor device and method for controlling operation thereof

Semiconductor device and method of controlling the same

Memory controller for multilevel cell memory