TREA

Hideyuki Asakawa

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  • Tokyo, JP
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Patents Grantslast 30 patents

  • Information Patent Grant

    PLL (Phase-Locked Loop) circuit
    • Patent number 7,050,520
    • Issue date May 23, 2006
    • NEC Corporation
    • Hideyuki Asakawa
    • H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

  • Information Patent Application

    Ring network system
    • Publication number 20030223380
    • Publication date Dec 4, 2003
    • NEC Corporation
    • Hideyuki Asakawa
    • H04 - ELECTRIC COMMUNICATION TECHNIQUE
  • Information Patent Application

    PLL (Phase-Locked Loop) circuit
    • Publication number 20020181640
    • Publication date Dec 5, 2002
    • Hideyuki Asakawa
    • H03 - BASIC ELECTRONIC CIRCUITRY