Hideyuki Iino

Person

Kawasaki, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Reset control system and method
- Patent number 6,877,112
- Issue date Apr 5, 2005
- Fujitsu Limited
- Hideyuki Iino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined data processing device having improved hardware control o...
- Patent number 5,822,557
- Issue date Oct 13, 1998
- Fujitsu Limited
- Seiji Suetake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system, memory access device and method including s...
- Patent number 5,809,552
- Issue date Sep 15, 1998
- Fujitsu Limited
- Koichi Kuroiwa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple bank structured memory access device having flexible setti...
- Patent number 5,768,559
- Issue date Jun 16, 1998
- Fujitsu Limited
- Hideyuki Iino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor for performing an arithmetic operation by automatically...
- Patent number 5,742,839
- Issue date Apr 21, 1998
- Fujitsu Limited
- Seiji Suetake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing apparatus for executing a vector operation under co...
- Patent number 5,742,842
- Issue date Apr 21, 1998
- Fujitsu Limited
- Seiji Suetake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System including processor and cache memory and method of controlli...
- Patent number 5,724,548
- Issue date Mar 3, 1998
- Fujitsu Limited
- Hiromasa Takahashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory accessing device for a pipeline information processing system
- Patent number 5,699,553
- Issue date Dec 16, 1997
- Fujitsu Limited
- Hideyuki Iino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having test circuit
- Patent number 5,654,972
- Issue date Aug 5, 1997
- Fujitsu Limited
- Koichi Kuroiwa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor system including an index buffer circuit and a translatio...
- Patent number 5,644,748
- Issue date Jul 1, 1997
- Fujitsu Limited
- Shinichi Utsunomiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system employing pipeline process for accessing memory banks
- Patent number 5,586,282
- Issue date Dec 17, 1996
- Fujitsu Limited
- Hideyuki Iino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic operation unit and memory accessing device for accessing...
- Patent number 5,551,010
- Issue date Aug 27, 1996
- Fujitsu Limited
- Hideyuki Iino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus controller
- Patent number 5,526,494
- Issue date Jun 11, 1996
- Fujitsu Limited
- Hideyuki Iino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct memory access controller with expedited error control
- Patent number 5,056,011
- Issue date Oct 8, 1991
- Fujitsu Limited
- Akihiro Yoshitake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock circuit having a clocked output buffer
- Patent number 4,929,854
- Issue date May 29, 1990
- Fujitsu Limited
- Hideyuki Iino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit having a DC test function
- Patent number 4,904,883
- Issue date Feb 27, 1990
- Fujitsu Limited
- Hideyuki Iino
- G01 - MEASURING TESTING

Hideyuki Iino

Person

Patents Grantslast 30 patents

Reset control system and method

Pipelined data processing device having improved hardware control o...

Data processing system, memory access device and method including s...

Multiple bank structured memory access device having flexible setti...

Coprocessor for performing an arithmetic operation by automatically...

Data processing apparatus for executing a vector operation under co...

System including processor and cache memory and method of controlli...

Memory accessing device for a pipeline information processing system

Processor having test circuit

Processor system including an index buffer circuit and a translatio...

Memory system employing pipeline process for accessing memory banks

Arithmetic operation unit and memory accessing device for accessing...

Bus controller

Direct memory access controller with expedited error control

Clock circuit having a clocked output buffer

Semiconductor integrated circuit having a DC test function