Hideyuki Okabe

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Kanagawa, JP

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Patents Grantslast 30 patents

Information Patent Grant
Method of supporting layout design of semiconductor integrated circuit
- Patent number 8,499,268
- Issue date Jul 30, 2013
- Renesas Electronics Corporation
- Hideyuki Okabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout design program, layout design device and layout design metho...
- Patent number 7,516,434
- Issue date Apr 7, 2009
- NEC Electronics Corporation
- Hideyuki Okabe
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF SUPPORTING LAYOUT DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT
- Publication number 20120221992
- Publication date Aug 30, 2012
- RENESAS ELECTRONICS CORPORATION
- Hideyuki OKABE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Layout design program, layout design device and layout design metho...
- Publication number 20060265678
- Publication date Nov 23, 2006
- NEC Electronics Corporation
- Hideyuki Okabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit verification method, verification apparatus, and...
- Publication number 20060117283
- Publication date Jun 1, 2006
- NEC Electronics Corporation
- Tetsuya Katou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for automatic arrangement and wiring for a sem...
- Publication number 20030135837
- Publication date Jul 17, 2003
- Hideyuki Okabe
- G06 - COMPUTING CALCULATING COUNTING