Hiranmay BISWAS

Person

Biswashati Bazar, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Power grid, IC and method for placing power grid
- Patent number 12,067,337
- Issue date Aug 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of forming semiconductor device
- Patent number 12,019,972
- Issue date Jun 25, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Kuo-Nan Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit and method of generating integrated circuit layout
- Patent number 11,908,853
- Issue date Feb 20, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Fong-Yuan Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of forming semiconductor device
- Patent number 11,651,136
- Issue date May 16, 2023
- Taiwan Semiconductor Manufacturing Company Ltd.
- Kuo-Nan Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit and method of generating integrated circuit layout
- Patent number 11,552,068
- Issue date Jan 10, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Fong-Yuan Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of fabricating semiconductor device including standard-cell-...
- Patent number 11,347,922
- Issue date May 31, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of forming semiconductor device
- Patent number 11,227,093
- Issue date Jan 18, 2022
- Taiwan Semiconductor Manufacturing Company Ltd.
- Kuo-Nan Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design method, system and computer program product
- Patent number 11,205,032
- Issue date Dec 21, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chin-Shen Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Merged pillar structures and method of generating layout diagram of...
- Patent number 11,157,677
- Issue date Oct 26, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of generating layout diagram including dummy pattern convers...
- Patent number 11,087,063
- Issue date Aug 10, 2021
- Taiwan Semiconductor Manufacturing Company Ltd.
- Ritesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power grid, IC and method for placing power grid
- Patent number 11,068,638
- Issue date Jul 20, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated device and method of forming the same
- Patent number 10,977,415
- Issue date Apr 13, 2021
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit and method of generating integrated circuit layout
- Patent number 10,964,685
- Issue date Mar 30, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Fong-Yuan Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device including standard-cell-adapted power grid arr...
- Patent number 10,943,045
- Issue date Mar 9, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inter-cell leakage-reducing method of generating layout diagram and...
- Patent number 10,936,785
- Issue date Mar 2, 2021
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of forming semiconductor device
- Patent number 10,922,470
- Issue date Feb 16, 2021
- Taiwan Semiconductor Manufacturing Company Ltd.
- Kuo-Nan Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device including PG-aligned cells and method of gener...
- Patent number 10,878,163
- Issue date Dec 29, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for forming conductive grid of integrated circuit
- Patent number 10,867,103
- Issue date Dec 15, 2020
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power grid, IC and method for placing power grid
- Patent number 10,672,709
- Issue date Jun 2, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated device and method of forming the same
- Patent number 10,664,641
- Issue date May 26, 2020
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit and method of generating integrated circuit layout
- Patent number 10,515,944
- Issue date Dec 24, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd
- Fong-Yuan Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Merged pillar structures and method of generating layout diagram of...
- Patent number 10,515,178
- Issue date Dec 24, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for forming integrated device
- Patent number 10,509,888
- Issue date Dec 17, 2019
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of forming conductive grid of integrated circuit
- Patent number 10,360,337
- Issue date Jul 23, 2019
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hiranmay Biswas
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE
- Publication number 20230252219
- Publication date Aug 10, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- KUO-NAN YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT AND METHOD OF GENERATING INTEGRATED CIRCUIT LAYOUT
- Publication number 20230121153
- Publication date Apr 20, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Fong-Yuan CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE
- Publication number 20220129614
- Publication date Apr 28, 2022
- Taiwan Semiconductor Manufacturing company Ltd.
- KUO-NAN YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER GRID, IC AND METHOD FOR PLACING POWER GRID
- Publication number 20210342515
- Publication date Nov 4, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hiranmay BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT AND METHOD OF GENERATING INTEGRATED CIRCUIT LAYOUT
- Publication number 20210217743
- Publication date Jul 15, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Fong-Yuan CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING STANDARD-CELL-...
- Publication number 20210209283
- Publication date Jul 8, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hiranmay BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE
- Publication number 20210150117
- Publication date May 20, 2021
- Taiwan Semiconductor Manufacturing company Ltd.
- KUO-NAN YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER GRID, IC AND METHOD FOR PLACING POWER GRID
- Publication number 20200279812
- Publication date Sep 3, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hiranmay BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED DEVICE AND METHOD OF FORMING THE SAME
- Publication number 20200272782
- Publication date Aug 27, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- HIRANMAY BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MERGED PILLAR STRUCTURES AND METHOD OF GENERATING LAYOUT DIAGRAM OF...
- Publication number 20200175220
- Publication date Jun 4, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hiranmay BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT
- Publication number 20200134121
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- Chin-Shen LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT AND METHOD OF GENERATING INTEGRATED CIRCUIT LAYOUT
- Publication number 20200126967
- Publication date Apr 23, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Fong-Yuan CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTER-CELL LEAKAGE-REDUCING METHOD OF GENERATING LAYOUT DIAGRAM AND...
- Publication number 20200074042
- Publication date Mar 5, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- Hiranmay BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERS...
- Publication number 20200004915
- Publication date Jan 2, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ritesh KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR FORMING CONDUCTIVE GRID OF INTEGRATED CIRCUIT
- Publication number 20190332739
- Publication date Oct 31, 2019
- Taiwan Semiconductor Manufacturing company Ltd.
- HIRANMAY BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING STANDARD-CELL-ADAPTED POWER GRID AR...
- Publication number 20190236234
- Publication date Aug 1, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hiranmay BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED DEVICE AND METHOD OF FORMING THE SAME
- Publication number 20190163861
- Publication date May 30, 2019
- Taiwan Semiconductor Manufacturing company Ltd.
- HIRANMAY BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE
- Publication number 20190163863
- Publication date May 30, 2019
- Taiwan Semiconductor Manufacturing company Ltd.
- KUO-NAN YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FORMING CONDUCTIVE GRID OF INTEGRATED CIRCUIT
- Publication number 20190155981
- Publication date May 23, 2019
- Taiwan Semiconductor Manufacturing company Ltd.
- HIRANMAY BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT AND METHOD OF GENERATING INTEGRATED CIRCUIT LAYOUT
- Publication number 20190148352
- Publication date May 16, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Fong-Yuan CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MERGED PILLAR STRUCTURES AND METHOD OF GENERATING LAYOUT DIAGRAM OF...
- Publication number 20190065653
- Publication date Feb 28, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hiranmay BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING PG-ALIGNED CELLS AND METHOD OF GENER...
- Publication number 20190065659
- Publication date Feb 28, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hiranmay BISWAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER GRID, IC AND PLACEMENT METHOD FOR POWER GRID
- Publication number 20180166386
- Publication date Jun 14, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hiranmay BISWAS
- G06 - COMPUTING CALCULATING COUNTING

Hiranmay BISWAS

Person

Patents Grantslast 30 patents

Power grid, IC and method for placing power grid

Method and system of forming semiconductor device

Integrated circuit and method of generating integrated circuit layout

Method and system of forming semiconductor device

Integrated circuit and method of generating integrated circuit layout

Method of fabricating semiconductor device including standard-cell-...

Method and system of forming semiconductor device

Integrated circuit design method, system and computer program product

Merged pillar structures and method of generating layout diagram of...

Method of generating layout diagram including dummy pattern convers...

Power grid, IC and method for placing power grid

Integrated device and method of forming the same

Integrated circuit and method of generating integrated circuit layout

Semiconductor device including standard-cell-adapted power grid arr...

Inter-cell leakage-reducing method of generating layout diagram and...

Method and system of forming semiconductor device

Semiconductor device including PG-aligned cells and method of gener...

Method and system for forming conductive grid of integrated circuit

Power grid, IC and method for placing power grid

Integrated device and method of forming the same

Integrated circuit and method of generating integrated circuit layout

Merged pillar structures and method of generating layout diagram of...

System and method for forming integrated device

Method of forming conductive grid of integrated circuit

Patents Applicationslast 30 patents

METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE

INTEGRATED CIRCUIT AND METHOD OF GENERATING INTEGRATED CIRCUIT LAYOUT

METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE

POWER GRID, IC AND METHOD FOR PLACING POWER GRID

INTEGRATED CIRCUIT AND METHOD OF GENERATING INTEGRATED CIRCUIT LAYOUT

METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING STANDARD-CELL-...

METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE

POWER GRID, IC AND METHOD FOR PLACING POWER GRID

INTEGRATED DEVICE AND METHOD OF FORMING THE SAME

MERGED PILLAR STRUCTURES AND METHOD OF GENERATING LAYOUT DIAGRAM OF...

INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT

INTEGRATED CIRCUIT AND METHOD OF GENERATING INTEGRATED CIRCUIT LAYOUT

INTER-CELL LEAKAGE-REDUCING METHOD OF GENERATING LAYOUT DIAGRAM AND...

METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERS...

METHOD AND SYSTEM FOR FORMING CONDUCTIVE GRID OF INTEGRATED CIRCUIT

SEMICONDUCTOR DEVICE INCLUDING STANDARD-CELL-ADAPTED POWER GRID AR...

INTEGRATED DEVICE AND METHOD OF FORMING THE SAME

METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE

METHOD OF FORMING CONDUCTIVE GRID OF INTEGRATED CIRCUIT

INTEGRATED CIRCUIT AND METHOD OF GENERATING INTEGRATED CIRCUIT LAYOUT

MERGED PILLAR STRUCTURES AND METHOD OF GENERATING LAYOUT DIAGRAM OF...

SEMICONDUCTOR DEVICE INCLUDING PG-ALIGNED CELLS AND METHOD OF GENER...

POWER GRID, IC AND PLACEMENT METHOD FOR POWER GRID