Hiro Kinoshita

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Three-dimensional memory device having epitaxial germanium-containi...
- Patent number 10,121,794
- Issue date Nov 6, 2018
- SanDisk Technologies LLC
- Marika Gunji-Yoneoka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming 3D memory cells after word line replacement
- Patent number 9,716,101
- Issue date Jul 25, 2017
- SanDisk Technologies LLC
- Zhenyu Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
HTO offset for long leffective, better device performance
- Patent number 9,455,352
- Issue date Sep 27, 2016
- Cypress Semiconductor Corporation
- Ning Cheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Oro and orpro with bit line trench to suppress transport program di...
- Patent number 9,245,895
- Issue date Jan 26, 2016
- Cypress Semiconductor Corporation
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structures and methods for making NAND flash memory
- Patent number 9,224,475
- Issue date Dec 29, 2015
- SanDisk Technologies Inc.
- Jongsun Sel
- G11 - INFORMATION STORAGE
Information Patent Grant
HTO offset for long Leffective, better device performance
- Patent number 8,653,581
- Issue date Feb 18, 2014
- Spansion LLC
- Ning Cheng
- G11 - INFORMATION STORAGE
Information Patent Grant
HTO offset and BL trench process for memory device to improve devic...
- Patent number 8,330,209
- Issue date Dec 11, 2012
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ORO and ORPRO with bit line trench to suppress transport program di...
- Patent number 8,012,830
- Issue date Sep 6, 2011
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
HTO offset spacers and dip off process to define junction
- Patent number 7,943,983
- Issue date May 17, 2011
- Spansion LLC
- Huaqiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
HTO offset and BL trench process for memory device to improve devic...
- Patent number 7,935,596
- Issue date May 3, 2011
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of a polymer spacer and Si trench in a bitline junction of a fl...
- Patent number 7,906,807
- Issue date Mar 15, 2011
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of a polymer spacer and Si trench in a bitline junction of a fl...
- Patent number 7,776,688
- Issue date Aug 17, 2010
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE HAVING EPITAXIAL GERMANIUM-CONTAINI...
- Publication number 20170365613
- Publication date Dec 21, 2017
- SanDisk Technologies LLC
- Marika GUNJI-YONEOKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory Hole Last Boxim
- Publication number 20160343718
- Publication date Nov 24, 2016
- SANDISK TECHNOLOGIES INC.
- Zhenyu Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
- Publication number 20140167138
- Publication date Jun 19, 2014
- SPANSION LLC
- Ning Cheng
- G11 - INFORMATION STORAGE
Information Patent Application
Structures and Methods for Making NAND Flash Memory
- Publication number 20140054669
- Publication date Feb 27, 2014
- Jongsun Sel
- G11 - INFORMATION STORAGE
Information Patent Application
ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DI...
- Publication number 20110278660
- Publication date Nov 17, 2011
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVIC...
- Publication number 20110169069
- Publication date Jul 14, 2011
- SPANSION, LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...
- Publication number 20100264480
- Publication date Oct 21, 2010
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION
- Publication number 20100155785
- Publication date Jun 24, 2010
- SPANSION LLC
- Huaqiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVIC...
- Publication number 20100155816
- Publication date Jun 24, 2010
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
- Publication number 20100155817
- Publication date Jun 24, 2010
- SPANSION LLC
- Ning Cheng
- G11 - INFORMATION STORAGE
Information Patent Application
USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...
- Publication number 20090042378
- Publication date Feb 12, 2009
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DI...
- Publication number 20090039405
- Publication date Feb 12, 2009
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS

Hiro Kinoshita

Person

Patents Grantslast 30 patents

Three-dimensional memory device having epitaxial germanium-containi...

Forming 3D memory cells after word line replacement

HTO offset for long leffective, better device performance

Oro and orpro with bit line trench to suppress transport program di...

Structures and methods for making NAND flash memory

HTO offset for long Leffective, better device performance

HTO offset and BL trench process for memory device to improve devic...

ORO and ORPRO with bit line trench to suppress transport program di...

HTO offset spacers and dip off process to define junction

HTO offset and BL trench process for memory device to improve devic...

Use of a polymer spacer and Si trench in a bitline junction of a fl...

Use of a polymer spacer and Si trench in a bitline junction of a fl...

Patents Applicationslast 30 patents

THREE-DIMENSIONAL MEMORY DEVICE HAVING EPITAXIAL GERMANIUM-CONTAINI...

Memory Hole Last Boxim

HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE

Structures and Methods for Making NAND Flash Memory

ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DI...

HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVIC...

USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...

HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION

HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVIC...

HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE

USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...

ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DI...