Hiroki Iciki

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Ring systolic array system for synchronously performing matrix/neur...
- Patent number 5,600,843
- Issue date Feb 4, 1997
- Fujitsu Limited
- Hideki Kato
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel data processing system which efficiently performs matrix a...
- Patent number 5,544,336
- Issue date Aug 6, 1996
- Fujitsu Limited
- Hideki Kato
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel data processing system using a plurality of processing ele...
- Patent number 5,506,998
- Issue date Apr 9, 1996
- Fujitsu Limited
- Hideki Kato
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous control system for a neuro computer
- Patent number 5,369,731
- Issue date Nov 29, 1994
- Fujitsu Limited
- Daiki Masumoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neuron architecture
- Patent number 5,220,559
- Issue date Jun 15, 1993
- Fujitsu Limited
- Hiroyuki Tsuzuki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel data processing apparatus with signal skew compensation
- Patent number 5,220,660
- Issue date Jun 15, 1993
- Fujitsu Limited
- Hideki Yoshizawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error absorbing system in a neuron computer
- Patent number 5,216,746
- Issue date Jun 1, 1993
- Fujitsu Limited
- Hideki Yoshizawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neurocomputer with analog signal bus
- Patent number 5,131,072
- Issue date Jul 14, 1992
- Fujitsu, Ltd.
- Hideki Yoshizawa
- G06 - COMPUTING CALCULATING COUNTING

Hiroki Iciki

Person

Patents Grantslast 30 patents

Ring systolic array system for synchronously performing matrix/neur...

Parallel data processing system which efficiently performs matrix a...

Parallel data processing system using a plurality of processing ele...

Asynchronous control system for a neuro computer

Neuron architecture

Parallel data processing apparatus with signal skew compensation

Error absorbing system in a neuron computer

Neurocomputer with analog signal bus