Hiromichi Kainoh

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Hadano, JP

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Patents Grantslast 30 patents

Information Patent Grant
Address translation buffer system and method for invalidating addre...
- Patent number 5,924,127
- Issue date Jul 13, 1999
- Hitachi, Ltd.
- Koji Kawamoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logical-to-real address translation based on selective use of first...
- Patent number 5,490,259
- Issue date Feb 6, 1996
- Hitachi, Ltd.
- Tohru Hiraoka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system having pipeline arithmetic/logic units
- Patent number 4,783,783
- Issue date Nov 8, 1988
- Hitachi, Ltd.
- Seiji Nagai
- G06 - COMPUTING CALCULATING COUNTING