Hiromitsu Yamada

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Hadano, JP

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Patents Grantslast 30 patents

Information Patent Grant
Hierarchical wiring method for a semiconductor integrated circuit
- Patent number 6,496,968
- Issue date Dec 17, 2002
- Hitachi, Ltd.
- Hiromitsu Yamada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of wiring semiconductor integrated circuit and semiconductor...
- Patent number 5,872,719
- Issue date Feb 16, 1999
- Hitachi, Ltd.
- Yoshiaki Miyazaki
- G06 - COMPUTING CALCULATING COUNTING