Hironobu TAOKA

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Simulation device and simulation program for simulating process usi...
- Patent number 9,582,617
- Issue date Feb 28, 2017
- Renesas Electronics Corporation
- Hironobu Taoka
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Mask data verification apparatus, design layout verification appara...
- Patent number 8,930,857
- Issue date Jan 6, 2015
- Renesas Electronics Corporation
- Hironobu Taoka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device which is subjected to optical proximity correc...
- Patent number 8,719,740
- Issue date May 6, 2014
- Renesas Electronics Corporation
- Hironobu Taoka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Lithography verification apparatus and lithography simulation program
- Patent number 8,464,192
- Issue date Jun 11, 2013
- Renesas Electronics Corporation
- Hironobu Taoka
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Semiconductor device including logic circuit having areas of differ...
- Patent number 8,458,627
- Issue date Jun 4, 2013
- Renesas Electronics Corporation
- Hironobu Taoka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device and its manufacturing method, semiconductor ma...
- Patent number 8,103,977
- Issue date Jan 24, 2012
- Renesas Electronics Corporation
- Hironobu Taoka
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD THEREOF, MASK FOR...
- Publication number 20130249597
- Publication date Sep 26, 2013
- RENESAS ELECTRONICS CORPORATION
- Hironobu TAOKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIMULATION DEVICE AND SIMULATION PROGRAM
- Publication number 20130185042
- Publication date Jul 18, 2013
- RENESAS ELECTRONICS CORPORATION
- Hironobu TAOKA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MASK DATA VERIFICATION APPARATUS, DESIGN LAYOUT VERIFICATION APPARA...
- Publication number 20120317524
- Publication date Dec 13, 2012
- Renesas Electronics Corporation
- Hironobu TAOKA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LITHOGRAPHY VERIFICATION APPARATUS AND LITHOGRAPHY SIMULATION PROGRAM
- Publication number 20120198393
- Publication date Aug 2, 2012
- Renesas Electronics Corporation
- Hironobu TAOKA
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, MASK FOR SEM...
- Publication number 20120091510
- Publication date Apr 19, 2012
- RENESAS ELECTRONICS CORPORATION
- Hironobu TAOKA
- E21 - EARTH DRILLING MINING
Information Patent Application
Semiconductor Device and its Manufacturing Method, Semiconductor Ma...
- Publication number 20090278569
- Publication date Nov 12, 2009
- Hironobu Taoka
- E21 - EARTH DRILLING MINING

Hironobu TAOKA

Person

Patents Grantslast 30 patents

Simulation device and simulation program for simulating process usi...

Mask data verification apparatus, design layout verification appara...

Semiconductor device which is subjected to optical proximity correc...

Lithography verification apparatus and lithography simulation program

Semiconductor device including logic circuit having areas of differ...

Semiconductor device and its manufacturing method, semiconductor ma...

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD THEREOF, MASK FOR...

SIMULATION DEVICE AND SIMULATION PROGRAM

MASK DATA VERIFICATION APPARATUS, DESIGN LAYOUT VERIFICATION APPARA...

LITHOGRAPHY VERIFICATION APPARATUS AND LITHOGRAPHY SIMULATION PROGRAM

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, MASK FOR SEM...

Semiconductor Device and its Manufacturing Method, Semiconductor Ma...