Hiroshi Ikejima

Person

Hong Kong, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,653,639
- Issue date Feb 18, 2014
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing layered chip package
- Patent number 8,652,877
- Issue date Feb 18, 2014
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,618,646
- Issue date Dec 31, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,541,887
- Issue date Sep 24, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing layered chip package
- Patent number 8,513,034
- Issue date Aug 20, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Layered chip package
- Patent number 8,466,562
- Issue date Jun 18, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ceramic capacitor and method of manufacturing same
- Patent number 8,462,482
- Issue date Jun 11, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method of manufacturing layered chip package
- Patent number 8,441,112
- Issue date May 14, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ceramic capacitor and method of manufacturing same
- Patent number 8,432,662
- Issue date Apr 30, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite layered chip package
- Patent number 8,426,979
- Issue date Apr 23, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,421,243
- Issue date Apr 16, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,362,602
- Issue date Jan 29, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,358,015
- Issue date Jan 22, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,344,494
- Issue date Jan 1, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package with wiring on the side surfaces
- Patent number 8,324,741
- Issue date Dec 4, 2012
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing the same
- Patent number 8,253,257
- Issue date Aug 28, 2012
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,203,215
- Issue date Jun 19, 2012
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,203,216
- Issue date Jun 19, 2012
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing ceramic capacitor
- Patent number 8,171,607
- Issue date May 8, 2012
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Layered chip package with heat sink
- Patent number 8,154,116
- Issue date Apr 10, 2012
- HeadwayTechnologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package with wiring on the side surfaces
- Patent number 7,968,374
- Issue date Jun 28, 2011
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 7,964,976
- Issue date Jun 21, 2011
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of manufacturing layered chip package
- Patent number 7,915,083
- Issue date Mar 29, 2011
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite layered chip package and method of manufacturing same
- Patent number 7,902,677
- Issue date Mar 8, 2011
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
COMPOSITE LAYERED CHIP PACKAGE
- Publication number 20130020723
- Publication date Jan 24, 2013
- SAE MAGNETICS (H. K) LTD.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20120313260
- Publication date Dec 13, 2012
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20120313259
- Publication date Dec 13, 2012
- SAE Magnetics (H.K.) Ltd.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20120256321
- Publication date Oct 11, 2012
- SAE MAGNETICS (H.K.) LTD.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20120187575
- Publication date Jul 26, 2012
- SAE MAGNETICS (H. K) LTD.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING LAYERED CHIP PACKAGE
- Publication number 20120142146
- Publication date Jun 7, 2012
- SAE MAGNETICS (H. K) LTD.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20120086130
- Publication date Apr 12, 2012
- SAE MAGNETICS (H. K) LTD.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING LAYERED CHIP PACKAGE
- Publication number 20120080782
- Publication date Apr 5, 2012
- SAE MAGNETICS (H.K.) LTD.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20120056333
- Publication date Mar 8, 2012
- SAE MAGNETICS (H. K) LTD.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20120032318
- Publication date Feb 9, 2012
- SAE MAGNETICS (H.K.) LTD.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered Chip Package and Method of Manufacturing Same
- Publication number 20120013024
- Publication date Jan 19, 2012
- SAE MAGNETICS (H. K) LTD.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered Chip Package and Method of Manufacturing Same
- Publication number 20120013025
- Publication date Jan 19, 2012
- SAE MAGNETICS (H. K) LTD.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20110316141
- Publication date Dec 29, 2011
- SAE MAGNETICS(H.K) LTD.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered chip package with wiring on the side surfaces
- Publication number 20110221073
- Publication date Sep 15, 2011
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of manufacturing layered chip package
- Publication number 20110201137
- Publication date Aug 18, 2011
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- G11 - INFORMATION STORAGE
Information Patent Application
Layered chip package and method of manufacturing same
- Publication number 20110068456
- Publication date Mar 24, 2011
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered chip package and method of manufacturing same
- Publication number 20100200977
- Publication date Aug 12, 2010
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CERAMIC CAPACITOR AND METHOD OF MANUFACTURING SAME
- Publication number 20100195262
- Publication date Aug 5, 2010
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CERAMIC CAPACITOR AND METHOD OF MANUFACTURING SAME
- Publication number 20100195264
- Publication date Aug 5, 2010
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING CERAMIC CAPACITOR
- Publication number 20100192343
- Publication date Aug 5, 2010
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered chip package with heat sink
- Publication number 20100109137
- Publication date May 6, 2010
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered chip package and method of manufacturing same
- Publication number 20100044879
- Publication date Feb 25, 2010
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka Sasaki
- G11 - INFORMATION STORAGE

Hiroshi Ikejima

Person

Patents Grantslast 30 patents

Layered chip package and method of manufacturing same

Method of manufacturing layered chip package

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same

Method of manufacturing layered chip package

Layered chip package

Ceramic capacitor and method of manufacturing same

Method of manufacturing layered chip package

Ceramic capacitor and method of manufacturing same

Composite layered chip package

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same

Layered chip package with wiring on the side surfaces

Layered chip package and method of manufacturing the same

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same

Method of manufacturing ceramic capacitor

Layered chip package with heat sink

Layered chip package with wiring on the side surfaces

Layered chip package and method of manufacturing same

Method of manufacturing layered chip package

Composite layered chip package and method of manufacturing same

Patents Applicationslast 30 patents

COMPOSITE LAYERED CHIP PACKAGE

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME

METHOD OF MANUFACTURING LAYERED CHIP PACKAGE

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME

METHOD OF MANUFACTURING LAYERED CHIP PACKAGE

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME

Layered Chip Package and Method of Manufacturing Same

Layered Chip Package and Method of Manufacturing Same

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME

Layered chip package with wiring on the side surfaces

Method of manufacturing layered chip package

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same

CERAMIC CAPACITOR AND METHOD OF MANUFACTURING SAME

CERAMIC CAPACITOR AND METHOD OF MANUFACTURING SAME

METHOD OF MANUFACTURING CERAMIC CAPACITOR

Layered chip package with heat sink

Layered chip package and method of manufacturing same