Hiroyuki TANAKA

Person

Yokkaichi, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Three-dimensional memory device with off-center or reverse slope st...
- Patent number 11,991,881
- Issue date May 21, 2024
- SanDisk Technologies LLC
- Hiroyuki Tanaka
Information Patent Grant
Three-dimensional memory device containing direct contact drain-sel...
- Patent number 11,121,149
- Issue date Sep 14, 2021
- SanDisk Technologies LLC
- Hiroyuki Tanaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D NAND device with five-folded memory stack structure configuration
- Patent number 10,403,632
- Issue date Sep 3, 2019
- SanDisk Technologies LLC
- Hiroyuki Ogawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional memory device containing structurally reinforced...
- Patent number 10,115,730
- Issue date Oct 30, 2018
- SanDisk Technologies LLC
- Ashish Baraskar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D NAND device with five-folded memory stack structure configuration
- Patent number 9,899,399
- Issue date Feb 20, 2018
- SanDisk Technologies LLC
- Hiroyuki Ogawa
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE HAVING CONTROLLED LATERAL ISOLATION...
- Publication number 20250024681
- Publication date Jan 16, 2025
- WESTERN DIGITAL TECHNOLOGIES, INC.,
- Takaaki IWAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A MID-STACK SOURCE LAYER...
- Publication number 20240363165
- Publication date Oct 31, 2024
- SANDISK TECHNOLOGIES LLC
- Kento SAKANE
- G11 - INFORMATION STORAGE
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SILICON OXYCARBIDE LINER...
- Publication number 20240260266
- Publication date Aug 1, 2024
- SANDISK TECHNOLOGIES LLC
- Naohiro HOSODA
Information Patent Application
MEMORY DEVICE CONTAINING CONSTRICTED CHANNEL ENDS AND METHODS OF MA...
- Publication number 20240215244
- Publication date Jun 27, 2024
- SANDISK TECHNOLOGIES LLC
- Hiroyuki TANAKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE WITH OFF-CENTER OR REVERSE SLOPE ST...
- Publication number 20220328512
- Publication date Oct 13, 2022
- SANDISK TECHNOLOGIES LLC
- Hiroyuki TANAKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DIRECT CONTACT DRAIN-SEL...
- Publication number 20200051995
- Publication date Feb 13, 2020
- SANDISK TECHNOLOGIES LLC
- Hiroyuki TANAKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D NAND DEVICE WITH FIVE-FOLDED MEMORY STACK STRUCTURE CONFIGURATION
- Publication number 20180158834
- Publication date Jun 7, 2018
- SanDisk Technologies LLC
- Hiroyuki OGAWA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D NAND DEVICE WITH FIVE-FOLDED MEMORY STACK STRUCTURE CONFIGURATION
- Publication number 20170125433
- Publication date May 4, 2017
- SanDisk Technologies LLC
- Hiroyuki OGAWA
- H01 - BASIC ELECTRIC ELEMENTS

Hiroyuki TANAKA

Person

Patents Grantslast 30 patents

Three-dimensional memory device with off-center or reverse slope st...

Three-dimensional memory device containing direct contact drain-sel...

3D NAND device with five-folded memory stack structure configuration

Three-dimensional memory device containing structurally reinforced...

3D NAND device with five-folded memory stack structure configuration

Patents Applicationslast 30 patents

THREE-DIMENSIONAL MEMORY DEVICE HAVING CONTROLLED LATERAL ISOLATION...

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A MID-STACK SOURCE LAYER...

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SILICON OXYCARBIDE LINER...

MEMORY DEVICE CONTAINING CONSTRICTED CHANNEL ENDS AND METHODS OF MA...

THREE-DIMENSIONAL MEMORY DEVICE WITH OFF-CENTER OR REVERSE SLOPE ST...

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DIRECT CONTACT DRAIN-SEL...

3D NAND DEVICE WITH FIVE-FOLDED MEMORY STACK STRUCTURE CONFIGURATION

3D NAND DEVICE WITH FIVE-FOLDED MEMORY STACK STRUCTURE CONFIGURATION