Hiroyuki Tsujikawa

Person

Kusatsu, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device, method of generating pattern for semiconducto...
- Patent number 7,911,027
- Issue date Mar 22, 2011
- Panasonic Corporation
- Mitsumi Itoh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device method of generating semiconductor device patt...
- Patent number 7,307,333
- Issue date Dec 11, 2007
- Matsushita Electric Industrial Co., Ltd.
- Mitsumi Itoh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design method for semiconductor integrated circuit suppressing powe...
- Patent number 7,278,124
- Issue date Oct 2, 2007
- Matsushita Electric Industrial Co., Ltd.
- Kenji Shimazaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device, method of generating pattern for semiconducto...
- Patent number 7,171,645
- Issue date Jan 30, 2007
- Matsushita Electric Industrial Co., Ltd.
- Mitsumi Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mask pattern inspecting method, inspection apparatus, inspecting da...
- Patent number 7,114,144
- Issue date Sep 26, 2006
- Matsushita Electric Industrial Co., Ltd.
- Shinya Tokunaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device, method of generating pattern for semiconducto...
- Patent number 7,062,732
- Issue date Jun 13, 2006
- Matsushita Electric Industrial Co., Ltd.
- Mitsumi Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of analyzing electromagnetic interference
- Patent number 7,039,572
- Issue date May 2, 2006
- Matsushita Electric Industrial Co., Ltd.
- Hidetoshi Narahara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of analyzing electromagnetic interference
- Patent number 6,959,250
- Issue date Oct 25, 2005
- Matsushita Electric Industrial Co., Ltd.
- Kenji Shimazaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection structure and method for designing the same
- Patent number 6,943,129
- Issue date Sep 13, 2005
- Matsushita Electric Industrial Co., Ltd.
- Chihiro Hyoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for analyzing electromagnetic interference
- Patent number 6,876,210
- Issue date Apr 5, 2005
- Matsushita Electric Industrial Co., Ltd.
- Kenji Shimazaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electromagnetic disturbance analysis method and apparatus and semic...
- Patent number 6,810,340
- Issue date Oct 26, 2004
- Matsushita Electric Industrial Co., Ltd.
- Kenji Shimazaki
- G01 - MEASURING TESTING
Information Patent Grant
Method for optimizing electromagnetic interference and method for a...
- Patent number 6,782,347
- Issue date Aug 24, 2004
- Matsushita Electric Industrial Co., Ltd.
- Shouzou Hirano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electromagnetic interference analysis method and apparatus
- Patent number 6,754,598
- Issue date Jun 22, 2004
- Matsushita Electric Industrial Co., Ltd.
- Kenji Shimazaki
- G01 - MEASURING TESTING
Information Patent Grant
Latch-up verifying method and latch-up verifying apparatus capable...
- Patent number 6,718,528
- Issue date Apr 6, 2004
- Matsushita Electric Industrial Co. Ltd.
- Shinichi Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection structure and method for designing the same
- Patent number 6,710,449
- Issue date Mar 23, 2004
- Matsushita Electric Industrial Co., Ltd.
- Chihiro Hyoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Latch-up verifying method and latch-up verifying apparatus capable...
- Patent number 6,490,709
- Issue date Dec 3, 2002
- Matsushita Electric Industrial Co., Ltd.
- Shinichi Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pattern forming method
- Patent number 6,434,730
- Issue date Aug 13, 2002
- Matsushita Electric Industrial Co., Ltd.
- Mitsumi Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mask pattern correction process, photomask and semiconductor integr...
- Patent number 6,303,251
- Issue date Oct 16, 2001
- Matsushita Electric Industrial Co., Ltd.
- Kiyohito Mukai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Semiconductor device geometrical pattern correction process and geo...
- Patent number 6,183,920
- Issue date Feb 6, 2001
- Matsushita Electric Industrial Co., Ltd.
- Hiroyuki Tsujikawa
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor device, method of generating pattern for semiconducto...
- Publication number 20070187777
- Publication date Aug 16, 2007
- Matsushita Electric Industrial Co., Ltd.
- Mitsumi Itoh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE LAYOUT INSPECTION METHOD
- Publication number 20070136702
- Publication date Jun 14, 2007
- Matsushita Electric Industrial Co., Ltd.
- Kiyohito MUKAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mask pattern inspecting method, inspection apparatus, inspecting da...
- Publication number 20070009147
- Publication date Jan 11, 2007
- Matsushita Electric Industrial Co., Ltd.
- Shinya Tokunaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of analyzing operation of semiconductor integrated circuit d...
- Publication number 20060091550
- Publication date May 4, 2006
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Kenji Shimazaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit device, method of enerating patter...
- Publication number 20050224914
- Publication date Oct 13, 2005
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Kiyohito Mukai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layout data verification method, mask pattern verification method a...
- Publication number 20050204327
- Publication date Sep 15, 2005
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Kiyohito Mukai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Design method for semiconductor integrated circuit suppressing powe...
- Publication number 20050149894
- Publication date Jul 7, 2005
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Kenji Shimazaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for analyzing power supply noise of semiconductor integrated...
- Publication number 20050114054
- Publication date May 26, 2005
- Kenji Shimazaki
- G01 - MEASURING TESTING
Information Patent Application
Semiconductor device method of generating semiconductor device patt...
- Publication number 20050017320
- Publication date Jan 27, 2005
- Mitsumi Itoh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Substrate noise analyzing method for semiconductor integrated circu...
- Publication number 20050005254
- Publication date Jan 6, 2005
- Matsushita Electric Industrial Co. Ltd.
- Shouzou Hirano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mask pattern inspecting method, inspection apparatus, inspecting da...
- Publication number 20040148584
- Publication date Jul 29, 2004
- Shinya Tokunaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor device layout inspection method
- Publication number 20040139407
- Publication date Jul 15, 2004
- Kiyohito Mukai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor device, method of generating pattern for semiconducto...
- Publication number 20040139412
- Publication date Jul 15, 2004
- Mitsumi Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor device, method of generating pattern for semiconducto...
- Publication number 20040102034
- Publication date May 27, 2004
- Mitsumi Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interconnection structure and method for designing the same
- Publication number 20040101996
- Publication date May 27, 2004
- Matsushita Electric Industrial Co., Ltd.
- Chihiro Hyoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Latch-up verifying method and latch-up verifying apparatus capable...
- Publication number 20030074641
- Publication date Apr 17, 2003
- Shinichi Kimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Electromagnetic interference analysis method and apparatus
- Publication number 20030057966
- Publication date Mar 27, 2003
- Kenji Shimazaki
- G01 - MEASURING TESTING
Information Patent Application
Interconnection structure and method for designing the same
- Publication number 20030049945
- Publication date Mar 13, 2003
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Chihiro Hyoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electromagnetic disturbance analysis method and apparatus and semic...
- Publication number 20020147553
- Publication date Oct 10, 2002
- Kenji Shimazaki
- G01 - MEASURING TESTING
Information Patent Application
Semiconductor device, method of creating pattern of the same, metho...
- Publication number 20020109205
- Publication date Aug 15, 2002
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Masatoshi Sawada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for analyzing electromagnetic interference
- Publication number 20020075018
- Publication date Jun 20, 2002
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Kenji Shimazaki
- G01 - MEASURING TESTING
Information Patent Application
Method for optimizing electromagnetic interference and method for a...
- Publication number 20020065643
- Publication date May 30, 2002
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Shouzou Hirano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Electromagnetic interference analysis method and apparatus
- Publication number 20020045995
- Publication date Apr 18, 2002
- Kenji Shimazaki
- G01 - MEASURING TESTING

Hiroyuki Tsujikawa

Person

Patents Grantslast 30 patents

Semiconductor device, method of generating pattern for semiconducto...

Semiconductor device method of generating semiconductor device patt...

Design method for semiconductor integrated circuit suppressing powe...

Semiconductor device, method of generating pattern for semiconducto...

Mask pattern inspecting method, inspection apparatus, inspecting da...

Semiconductor device, method of generating pattern for semiconducto...

Method of analyzing electromagnetic interference

Method of analyzing electromagnetic interference

Interconnection structure and method for designing the same

Method and apparatus for analyzing electromagnetic interference

Electromagnetic disturbance analysis method and apparatus and semic...

Method for optimizing electromagnetic interference and method for a...

Electromagnetic interference analysis method and apparatus

Latch-up verifying method and latch-up verifying apparatus capable...

Interconnection structure and method for designing the same

Latch-up verifying method and latch-up verifying apparatus capable...

Pattern forming method

Mask pattern correction process, photomask and semiconductor integr...

Semiconductor device geometrical pattern correction process and geo...

Patents Applicationslast 30 patents

Semiconductor device, method of generating pattern for semiconducto...

SEMICONDUCTOR DEVICE LAYOUT INSPECTION METHOD

Mask pattern inspecting method, inspection apparatus, inspecting da...

Method of analyzing operation of semiconductor integrated circuit d...

Semiconductor integrated circuit device, method of enerating patter...

Layout data verification method, mask pattern verification method a...

Design method for semiconductor integrated circuit suppressing powe...

Method for analyzing power supply noise of semiconductor integrated...

Semiconductor device method of generating semiconductor device patt...

Substrate noise analyzing method for semiconductor integrated circu...

Mask pattern inspecting method, inspection apparatus, inspecting da...

Semiconductor device layout inspection method

Semiconductor device, method of generating pattern for semiconducto...

Semiconductor device, method of generating pattern for semiconducto...

Interconnection structure and method for designing the same

Latch-up verifying method and latch-up verifying apparatus capable...

Electromagnetic interference analysis method and apparatus

Interconnection structure and method for designing the same

Electromagnetic disturbance analysis method and apparatus and semic...

Semiconductor device, method of creating pattern of the same, metho...

Method and apparatus for analyzing electromagnetic interference

Method for optimizing electromagnetic interference and method for a...

Electromagnetic interference analysis method and apparatus