Hiroyuki Yoshida

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Plano, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Reduced size plate layer improves misalignments for CUB DRAM
- Patent number 6,873,001
- Issue date Mar 29, 2005
- Texas Instruments Incorporated
- Toshiyuki Nagata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Relaxed layout for storage nodes for dynamic random access memories
- Patent number 6,166,941
- Issue date Dec 26, 2000
- Texas Instruments Incorporated
- Hiroyuki Yoshida
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Reduced size plate layer improves misalignments in CUB DRAM
- Publication number 20050030804
- Publication date Feb 10, 2005
- Toshiyuki Nagata
- H01 - BASIC ELECTRIC ELEMENTS