Hitoaki NISHIWAKI

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Kasugai, JP

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Patents Grantslast 30 patents

Information Patent Grant
Memory interface circuit and timing adjusting method
- Patent number 8,982,650
- Issue date Mar 17, 2015
- Fujitsu Semiconductor Limited
- Hitoaki Nishiwaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device with mechanism for leak defect detection
- Patent number 7,471,099
- Issue date Dec 30, 2008
- Fujitsu Limited
- Yuji Kurita
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY INTERFACE CIRCUIT AND TIMING ADJUSTING METHOD
- Publication number 20130070544
- Publication date Mar 21, 2013
- FUJITSU SEMICONDUCTOR LIMITED
- Hitoaki NISHIWAKI
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device with mechanism for leak defect detection
- Publication number 20060139822
- Publication date Jun 29, 2006
- FUJITSU LIMITED
- Yuji Kurita
- G01 - MEASURING TESTING