Hitoshi Okamura

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Method of designing a semiconductor integrated circuit device in a...
- Patent number 6,510,549
- Issue date Jan 21, 2003
- NEC Corporation
- Hitoshi Okamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
BiCMOS logical integrated circuit
- Patent number 6,037,637
- Issue date Mar 14, 2000
- NEC Corporation
- Hitoshi Okamura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
BiMOS integrated circuit
- Patent number 5,917,342
- Issue date Jun 29, 1999
- NEC Corporation
- Hitoshi Okamura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor static random access memory device having memory cell...
- Patent number 5,771,190
- Issue date Jun 23, 1998
- NEC Corporation
- Hitoshi Okamura
- G11 - INFORMATION STORAGE
Information Patent Grant
BiCMOS logic gate
- Patent number 5,739,703
- Issue date Apr 14, 1998
- NEC Corporation
- Hitoshi Okamura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
BiCMOS logic circuit with bipolar base clamping
- Patent number 5,670,893
- Issue date Sep 23, 1997
- NEC Corporation
- Hitoshi Okamura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power supply circuit for non-threshold logic circuit
- Patent number 5,619,123
- Issue date Apr 8, 1997
- NEC Corporation
- Hitoshi Okamura
- G05 - CONTROLLING REGULATING
Information Patent Grant
Charge pump circuit for boosting voltage
- Patent number 5,604,671
- Issue date Feb 18, 1997
- NEC Corporation
- Hitoshi Okamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Bicmos push-pull type logic apparatus with voltage clamp circuit an...
- Patent number 5,559,451
- Issue date Sep 24, 1996
- NEC Corporation
- Hitoshi Okamura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor integrated circuit device having clock signal wiring...
- Patent number 5,532,500
- Issue date Jul 2, 1996
- NEC Corporation
- Hitoshi Okamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device capable of reducing a clock skew in a pluralit...
- Patent number 5,521,541
- Issue date May 28, 1996
- NEC Corporation
- Hitoshi Okamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read write memory with negative feedback-controlled dummy memory ci...
- Patent number 5,473,568
- Issue date Dec 5, 1995
- NEC Corporation
- Hitoshi Okamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semicustom-made semiconductor integrated circuit having interface c...
- Patent number 5,067,003
- Issue date Nov 19, 1991
- NEC Corporation
- Hitoshi Okamura
- H01 - BASIC ELECTRIC ELEMENTS

Hitoshi Okamura

Person

Patents Grantslast 30 patents

Method of designing a semiconductor integrated circuit device in a...

BiCMOS logical integrated circuit

BiMOS integrated circuit

Semiconductor static random access memory device having memory cell...

BiCMOS logic gate

BiCMOS logic circuit with bipolar base clamping

Power supply circuit for non-threshold logic circuit

Charge pump circuit for boosting voltage

Bicmos push-pull type logic apparatus with voltage clamp circuit an...

Semiconductor integrated circuit device having clock signal wiring...

Semiconductor device capable of reducing a clock skew in a pluralit...

Read write memory with negative feedback-controlled dummy memory ci...

Semicustom-made semiconductor integrated circuit having interface c...