Ho-Yung David Hwang

Person

Hsinchu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for supplying and dispensing bubble-free photolit...
- Patent number 12,025,917
- Issue date Jul 2, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Wen-Zhan Zhou
- B67 - OPENING, CLOSING OR CLEANING BOTTLES, JARS OR SIMILAR CONTAINERS LIQUID...
Information Patent Grant
Adaptive baking method
- Patent number 11,204,200
- Issue date Dec 21, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Tzung-Chen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for supplying and dispensing bubble-free photolit...
- Patent number 10,558,120
- Issue date Feb 11, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Wen-Zhan Zhou
- B67 - OPENING, CLOSING OR CLEANING BOTTLES, JARS OR SIMILAR CONTAINERS LIQUID...
Information Patent Grant
Two-dimensional marks
- Patent number 10,274,839
- Issue date Apr 30, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Zhan Zhou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Adaptive baking system and method of using the same
- Patent number 10,006,717
- Issue date Jun 26, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd
- Tzung-Chen Wu
- F27 - FURNACES KILNS OVENS RETORTS
Information Patent Grant
System and method for supplying and dispensing bubble-free photolit...
- Patent number 9,817,315
- Issue date Nov 14, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Wen-Zhan Zhou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Hybrid focus-exposure matrix
- Patent number 9,690,212
- Issue date Jun 27, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Zhan Zhou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Reducing wafer distortion through a high CTE layer
- Patent number 9,153,435
- Issue date Oct 6, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon wafer strength enhancement
- Patent number 9,123,671
- Issue date Sep 1, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate breakdown voltage improvement for group III-nitride on a...
- Patent number 8,791,504
- Issue date Jul 29, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-nitride growth method on silicon substrate
- Patent number 8,772,831
- Issue date Jul 8, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- C30 - CRYSTAL GROWTH
Information Patent Grant
Reducing wafer distortion through a high CTE layer
- Patent number 8,723,185
- Issue date May 13, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET device and method of manufacturing same
- Patent number 8,624,326
- Issue date Jan 7, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing wafer distortion through a low CTE layer
- Patent number 8,476,146
- Issue date Jul 2, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLIT...
- Publication number 20230384680
- Publication date Nov 30, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Zhan Zhou
- B67 - OPENING, CLOSING OR CLEANING BOTTLES, JARS OR SIMILAR CONTAINERS LIQUID...
Information Patent Application
ADAPTIVE BAKING METHOD
- Publication number 20220074668
- Publication date Mar 10, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tzung-Chen WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLIT...
- Publication number 20200124967
- Publication date Apr 23, 2020
- Taiwan Semiconductor Manufacturing Co., LTD
- Wen-Zhan Zhou
- B67 - OPENING, CLOSING OR CLEANING BOTTLES, JARS OR SIMILAR CONTAINERS LIQUID...
Information Patent Application
ADAPTIVE BAKING METHOD
- Publication number 20180306514
- Publication date Oct 25, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tzung-Chen WU
- F27 - FURNACES KILNS OVENS RETORTS
Information Patent Application
SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLIT...
- Publication number 20180067395
- Publication date Mar 8, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Wen-Zhan Zhou
- B67 - OPENING, CLOSING OR CLEANING BOTTLES, JARS OR SIMILAR CONTAINERS LIQUID...
Information Patent Application
SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLIT...
- Publication number 20150261089
- Publication date Sep 17, 2015
- Taiwan Semiconductor Manufacturing Co., LTD
- Wen-Zhan Zhou
- B67 - OPENING, CLOSING OR CLEANING BOTTLES, JARS OR SIMILAR CONTAINERS LIQUID...
Information Patent Application
ADAPTIVE BAKING SYSTEM AND METHOD OF USING THE SAME
- Publication number 20150253083
- Publication date Sep 10, 2015
- TAIWAN SEMICONDUCTOR MANUFACTURING COMAPNY, LTD.
- Tzung-Chen WU
- F27 - FURNACES KILNS OVENS RETORTS
Information Patent Application
Two-Dimensional Marks
- Publication number 20140253901
- Publication date Sep 11, 2014
- Wen-Zhan Zhou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Hybrid Focus-Exposure Matrix
- Publication number 20140257761
- Publication date Sep 11, 2014
- Wen-Zhan Zhou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER
- Publication number 20140242768
- Publication date Aug 28, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER
- Publication number 20140242759
- Publication date Aug 28, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GALLIUM NITRIDE GROWTH METHOD ON SILICON SUBSTRATE
- Publication number 20130140525
- Publication date Jun 6, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming CHEN
- C30 - CRYSTAL GROWTH
Information Patent Application
NEW III-NITRIDE GROWTH METHOD ON SILICON SUBSTRATE
- Publication number 20130112939
- Publication date May 9, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming CHEN
- C30 - CRYSTAL GROWTH
Information Patent Application
SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A...
- Publication number 20130099243
- Publication date Apr 25, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FinFET Device And Method Of Manufacturing Same
- Publication number 20130099282
- Publication date Apr 25, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Apparatus for Forming a III-V Family Layer
- Publication number 20120238076
- Publication date Sep 20, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
SILICON WAFER STRENGTH ENHANCEMENT
- Publication number 20120168911
- Publication date Jul 5, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR FORMING A III-V FAMILY LAYER
- Publication number 20120149176
- Publication date Jun 14, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
REDUCING WAFER DISTORTION THROUGH A LOW CTE LAYER
- Publication number 20120138945
- Publication date Jun 7, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER
- Publication number 20120132921
- Publication date May 31, 2012
- TAWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Chi-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS

Ho-Yung David Hwang

Person

Patents Grantslast 30 patents

System and method for supplying and dispensing bubble-free photolit...

Adaptive baking method

System and method for supplying and dispensing bubble-free photolit...

Two-dimensional marks

Adaptive baking system and method of using the same

System and method for supplying and dispensing bubble-free photolit...

Hybrid focus-exposure matrix

Reducing wafer distortion through a high CTE layer

Silicon wafer strength enhancement

Substrate breakdown voltage improvement for group III-nitride on a...

III-nitride growth method on silicon substrate

Reducing wafer distortion through a high CTE layer

FinFET device and method of manufacturing same

Reducing wafer distortion through a low CTE layer

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLIT...

ADAPTIVE BAKING METHOD

SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLIT...

ADAPTIVE BAKING METHOD

SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLIT...

SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLIT...

ADAPTIVE BAKING SYSTEM AND METHOD OF USING THE SAME

Two-Dimensional Marks

Hybrid Focus-Exposure Matrix

REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER

REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER

GALLIUM NITRIDE GROWTH METHOD ON SILICON SUBSTRATE

NEW III-NITRIDE GROWTH METHOD ON SILICON SUBSTRATE

SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A...

FinFET Device And Method Of Manufacturing Same

Method and Apparatus for Forming a III-V Family Layer

SILICON WAFER STRENGTH ENHANCEMENT

METHOD AND APPARATUS FOR FORMING A III-V FAMILY LAYER

REDUCING WAFER DISTORTION THROUGH A LOW CTE LAYER

REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER