Hoe-sik Chung

Person

Seongnam, KR

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device capable of adjusting memory page size based on...
- Patent number 8,804,455
- Issue date Aug 12, 2014
- Samsung Electronics Co., Ltd.
- Hoon Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of detecting error in a semiconductor memory device
- Patent number 8,756,475
- Issue date Jun 17, 2014
- Samsung Electronics Co., Ltd.
- Hoe-Ju Chung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Stacked semiconductor apparatus with configurable vertical I/O
- Patent number 8,736,296
- Issue date May 27, 2014
- Samsung Electronics Co., Ltd.
- Hoe ju Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for selectively performing single-ended and diffe...
- Patent number 8,654,864
- Issue date Feb 18, 2014
- Samsung Electronics Co., Ltd.
- Hoe-ju Chung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for selectively performing single-ended and diffe...
- Patent number 8,446,988
- Issue date May 21, 2013
- Samsung Electronics Co., Ltd.
- Hoe-ju Chung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Semiconductor device capable of adjusting memory page size based on...
- Patent number 8,411,528
- Issue date Apr 2, 2013
- Samsung Electronics Co., Ltd.
- Hoon Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked memory module and system
- Patent number 8,369,123
- Issue date Feb 5, 2013
- Samsung Electronics Co., Ltd.
- Uk-Song Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
Data read circuit for phase change memory device and apparatuses in...
- Patent number 8,351,252
- Issue date Jan 8, 2013
- Samsung Electronics Co., Ltd.
- Hoe-Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked semiconductor memory device with compound read buffer
- Patent number 8,261,004
- Issue date Sep 4, 2012
- Samsung Electronics Co., Ltd.
- Hoe-Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked memory module and system
- Patent number 8,243,487
- Issue date Aug 14, 2012
- Samsung Electronics Co., Ltd.
- Uk-Song Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
Latency control circuit and method using queuing design method
- Patent number 8,230,140
- Issue date Jul 24, 2012
- Samsung Electronics Co., Ltd.
- Byung-Hoon Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Process variation compensated multi-chip memory package
- Patent number 8,223,524
- Issue date Jul 17, 2012
- Samsung Electronics Co., Ltd.
- Hoe-ju Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module, a memory system including a memory controller and a...
- Patent number 8,185,711
- Issue date May 22, 2012
- Samsung Electronics Co., Ltd.
- Jung-bae Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-chip package memory device
- Patent number 8,174,115
- Issue date May 8, 2012
- Samsung Electronics Co., Ltd.
- Hoe-Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Data parallelizing receiver
- Patent number 8,161,349
- Issue date Apr 17, 2012
- Samsung Electronics Co., Ltd.
- Hoe-Ju Chung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device having adaptive power function
- Patent number 8,122,302
- Issue date Feb 21, 2012
- Samsung Electronics Co., Ltd.
- Hoe Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system for seamless switching
- Patent number 8,117,485
- Issue date Feb 14, 2012
- Samsung Electronics Co., Ltd.
- Hoe-Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
System and device with error detection/correction process and metho...
- Patent number 8,112,680
- Issue date Feb 7, 2012
- Samsung Electronics Co., Ltd.
- Hoe-Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Termination circuits and semiconductor memory devices having the same
- Patent number 8,107,271
- Issue date Jan 31, 2012
- Samsung Electronics Co., Ltd.
- Kwang-Soo Park
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor memory devices with interface chips having memory chi...
- Patent number 8,102,688
- Issue date Jan 24, 2012
- Samsung Electronics Co., Ltd.
- Hoe-ju Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Process variation compensated multi-chip memory package
- Patent number 8,054,663
- Issue date Nov 8, 2011
- Samsung Electronics Co., Ltd.
- Hoe-ju Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for selectively performing single-ended and diffe...
- Patent number 8,050,332
- Issue date Nov 1, 2011
- Samsung Electronics Co., Ltd.
- Hoe-ju Chung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory device employing dual clocking for generating systematic cod...
- Patent number 8,046,665
- Issue date Oct 25, 2011
- Samsung Electronics Co., Ltd.
- Hoe-ju Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked memory module and system
- Patent number 8,031,505
- Issue date Oct 4, 2011
- Samsung Electronics Co., Ltd.
- Uk-Song Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for communicating data over communication channels
- Patent number 8,024,624
- Issue date Sep 20, 2011
- Samsung Electronics Co., Ltd.
- Hoe-Ju Chung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Semiconductor memory device
- Patent number 8,023,337
- Issue date Sep 20, 2011
- Samsung Electronics Co., Ltd.
- Hoe-Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked memory device
- Patent number 7,999,367
- Issue date Aug 16, 2011
- Samsung Electronics Co., Ltd.
- Uk-song Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked semiconductor apparatus with configurable vertical I/O
- Patent number 7,990,171
- Issue date Aug 2, 2011
- Samsung Electronics Co., Ltd.
- Hoe ju Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Latency control circuit and method using queuing design method
- Patent number 7,979,605
- Issue date Jul 12, 2011
- Samsung Electronics Co., Ltd.
- Byung-Hoon Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having ESD protection circuit and method of te...
- Patent number 7,960,984
- Issue date Jun 14, 2011
- Samsung Electronics Co., Ltd.
- Young-Don Choi
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING MEMORY PAGE SIZE BASED ON...
- Publication number 20130201778
- Publication date Aug 8, 2013
- Samsung Electronics Co., Ltd.
- Hoon Lee
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFE...
- Publication number 20130163692
- Publication date Jun 27, 2013
- Hoe-ju CHUNG
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Stacked Memory Module and System
- Publication number 20120300528
- Publication date Nov 29, 2012
- Uk-Song Kang
- G11 - INFORMATION STORAGE
Information Patent Application
PROCESS VARIATION COMPENSATED MULTI-CHIP MEMORY PACKAGE
- Publication number 20120051155
- Publication date Mar 1, 2012
- Samsung Electronics Co., Ltd.
- Hoe-Ju CHUNG
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFE...
- Publication number 20120039404
- Publication date Feb 16, 2012
- Samsung Electronics Co., Ltd.
- Hoe-ju CHUNG
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Stacked Memory Module and System
- Publication number 20110310649
- Publication date Dec 22, 2011
- Uk-Song Kang
- G11 - INFORMATION STORAGE
Information Patent Application
LATENCY CONTROL CIRCUIT AND METHOD USING QUEUING DESIGN METHOD
- Publication number 20110264874
- Publication date Oct 27, 2011
- Byung-Hoon JEONG
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED SEMICONDUCTOR APPARATUS WITH CONFIGURABLE VERTICAL I/O
- Publication number 20110248740
- Publication date Oct 13, 2011
- Samsung Electronics Co., Ltd.
- Hoe ju CHUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SEMICONDUCTOR MEMORY DEVICE WITH COMPOUND READ BUFFER
- Publication number 20110138087
- Publication date Jun 9, 2011
- Samsung Electronics Co., Ltd.
- Hoe-Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Application
Method of detecting error in a semiconductor memory device
- Publication number 20110107191
- Publication date May 5, 2011
- Hoe-Ju Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACK...
- Publication number 20110044084
- Publication date Feb 24, 2011
- Samsung Electronics Co., Ltd.
- Hoe-ju CHUNG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING PAGE SIZE
- Publication number 20100177572
- Publication date Jul 15, 2010
- Hoon LEE
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Chip Package Memory Device
- Publication number 20100164094
- Publication date Jul 1, 2010
- Hoe-Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device
- Publication number 20100118616
- Publication date May 13, 2010
- Hoe-Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked memory module and system
- Publication number 20100020583
- Publication date Jan 28, 2010
- Uk-Song Kang
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED SEMICONDUCTOR MEMORY DEVICE WITH COMPOUND READ BUFFER
- Publication number 20090319703
- Publication date Dec 24, 2009
- Samsung Electronics Co., Ltd.
- Hoe-Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Application
Memory System for seamless switching
- Publication number 20090282280
- Publication date Nov 12, 2009
- SAMSUNG ELECTRONICS CO., LTD.
- Hoe-Ju Chung
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICES WITH INTERFACE CHIPS HAVING MEMORY CHI...
- Publication number 20090237971
- Publication date Sep 24, 2009
- SAMSUNG ELECTRONICS CO., LTD.
- Hoe-ju Chung
- G11 - INFORMATION STORAGE
Information Patent Application
PROCESS VARIATION COMPENSATED MULTI-CHIP MEMORY PACKAGE
- Publication number 20090237970
- Publication date Sep 24, 2009
- Samsung Electronics Co., Ltd.
- Hoe-Ju CHUNG
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatuses and method for multi-level communication
- Publication number 20090122904
- Publication date May 14, 2009
- SAMSUNG ELECTRONICS CO., LTD.
- Young-chan Jang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD OF CONTROLLING INTERNAL VOLTAGE AND MULTI-CHIP PACKAGE MEMOR...
- Publication number 20090125687
- Publication date May 14, 2009
- Samsung Electronics Co., Ltd.
- Moon-sook PARK
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACK...
- Publication number 20090091962
- Publication date Apr 9, 2009
- Samsung Electronics Co., Ltd.
- Hoe-ju CHUNG
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED SEMICONDUCTOR APPARATUS WITH CONFIGURABLE VERTICAL I/O
- Publication number 20090091333
- Publication date Apr 9, 2009
- Samsung Electronics Co., Ltd.
- Hoe ju CHUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having ESD protection circuit and method of te...
- Publication number 20090085599
- Publication date Apr 2, 2009
- SAMSUNG ELECTRONICS CO., LTD.
- Young-Don Choi
- G01 - MEASURING TESTING
Information Patent Application
DELAY LOCKED LOOP CIRCUIT FOR A SYNCHRONOUS SEMICONDUCTOR MEMORY DE...
- Publication number 20090080272
- Publication date Mar 26, 2009
- JAE-JUN LEE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STACKED MEMORY DEVICE
- Publication number 20090039492
- Publication date Feb 12, 2009
- Samsung Electronics Co., Ltd.
- Uk-song KANG
- G11 - INFORMATION STORAGE
Information Patent Application
DATA PARALLELIZING RECEIVER
- Publication number 20090037800
- Publication date Feb 5, 2009
- Samsung Electronics Co., Ltd.
- Hoe-Ju CHUNG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFE...
- Publication number 20080273623
- Publication date Nov 6, 2008
- Samsung Electronics Co., Ltd.
- Hoe-ju CHUNG
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND DEVICE WITH ERROR DETECTION/CORRECTION PROCESS AND METHO...
- Publication number 20080256414
- Publication date Oct 16, 2008
- Samsung Electronics Co., Ltd.
- Hoe-Ju CHUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY LOCKED LOOP CIRCUIT FOR A SYNCHRONOUS SEMICONDUCTOR MEMORY DE...
- Publication number 20080219065
- Publication date Sep 11, 2008
- JAE-JUN LEE
- H03 - BASIC ELECTRONIC CIRCUITRY

Hoe-sik Chung

Person

Patents Grantslast 30 patents

Semiconductor device capable of adjusting memory page size based on...

Method of detecting error in a semiconductor memory device

Stacked semiconductor apparatus with configurable vertical I/O

System and method for selectively performing single-ended and diffe...

System and method for selectively performing single-ended and diffe...

Semiconductor device capable of adjusting memory page size based on...

Stacked memory module and system

Data read circuit for phase change memory device and apparatuses in...

Stacked semiconductor memory device with compound read buffer

Stacked memory module and system

Latency control circuit and method using queuing design method

Process variation compensated multi-chip memory package

Memory module, a memory system including a memory controller and a...

Multi-chip package memory device

Data parallelizing receiver

Semiconductor device having adaptive power function

Memory system for seamless switching

System and device with error detection/correction process and metho...

Termination circuits and semiconductor memory devices having the same

Semiconductor memory devices with interface chips having memory chi...

Process variation compensated multi-chip memory package

System and method for selectively performing single-ended and diffe...

Memory device employing dual clocking for generating systematic cod...

Stacked memory module and system

System and method for communicating data over communication channels

Semiconductor memory device

Stacked memory device

Stacked semiconductor apparatus with configurable vertical I/O

Latency control circuit and method using queuing design method

Semiconductor device having ESD protection circuit and method of te...

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING MEMORY PAGE SIZE BASED ON...

SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFE...

Stacked Memory Module and System

PROCESS VARIATION COMPENSATED MULTI-CHIP MEMORY PACKAGE

SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFE...

Stacked Memory Module and System

LATENCY CONTROL CIRCUIT AND METHOD USING QUEUING DESIGN METHOD

STACKED SEMICONDUCTOR APPARATUS WITH CONFIGURABLE VERTICAL I/O

STACKED SEMICONDUCTOR MEMORY DEVICE WITH COMPOUND READ BUFFER

Method of detecting error in a semiconductor memory device

MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACK...

SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING PAGE SIZE

Multi-Chip Package Memory Device

Semiconductor memory device

Stacked memory module and system

STACKED SEMICONDUCTOR MEMORY DEVICE WITH COMPOUND READ BUFFER

Memory System for seamless switching

SEMICONDUCTOR MEMORY DEVICES WITH INTERFACE CHIPS HAVING MEMORY CHI...

PROCESS VARIATION COMPENSATED MULTI-CHIP MEMORY PACKAGE

Apparatuses and method for multi-level communication

METHOD OF CONTROLLING INTERNAL VOLTAGE AND MULTI-CHIP PACKAGE MEMOR...

MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACK...

STACKED SEMICONDUCTOR APPARATUS WITH CONFIGURABLE VERTICAL I/O

Semiconductor device having ESD protection circuit and method of te...

DELAY LOCKED LOOP CIRCUIT FOR A SYNCHRONOUS SEMICONDUCTOR MEMORY DE...

STACKED MEMORY DEVICE

DATA PARALLELIZING RECEIVER

SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFE...

SYSTEM AND DEVICE WITH ERROR DETECTION/CORRECTION PROCESS AND METHO...

DELAY LOCKED LOOP CIRCUIT FOR A SYNCHRONOUS SEMICONDUCTOR MEMORY DE...