Hoki Kim

Person

San Ramon, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Three dimensional twisted bitline architecture for multi-port memory
- Patent number 7,885,138
- Issue date Feb 8, 2011
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrical antifuse with integrated sensor
- Patent number 7,714,326
- Issue date May 11, 2010
- International Business Machines Corporation
- Deok-kee Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic random access memory circuit, design structure and method
- Patent number 7,668,003
- Issue date Feb 23, 2010
- International Business Machines Corporation
- John E. Barth, Jr.
- G11 - INFORMATION STORAGE
Information Patent Grant
Floating body control in SOI DRAM
- Patent number 7,596,038
- Issue date Sep 29, 2009
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Floating body control in SOI DRAM
- Patent number 7,440,353
- Issue date Oct 21, 2008
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Three dimensional twisted bitline architecture for multi-port memory
- Patent number 7,286,437
- Issue date Oct 23, 2007
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Single cycle refresh of multi-port dynamic random access memory (DRAM)
- Patent number 7,145,829
- Issue date Dec 5, 2006
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM with self-resetting data path for reduced power consumption
- Patent number 7,136,317
- Issue date Nov 14, 2006
- International Business Machines Corporation
- David R. Hanson
- G11 - INFORMATION STORAGE
Information Patent Grant
Bi-mode sense amplifier with dual utilization of the reference cell...
- Patent number 7,046,565
- Issue date May 16, 2006
- International Business Machines Corporation
- John E. Barth, Jr.
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power manager for standby operation of memory system
- Patent number 7,046,572
- Issue date May 16, 2006
- International Business Machines Corporation
- David R. Hansen
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power manager for standby operation of a memory system
- Patent number 7,023,758
- Issue date Apr 4, 2006
- International Business Machines Corporation
- David R. Hanson
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-port memory architecture
- Patent number 6,990,025
- Issue date Jan 24, 2006
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic random access memory with smart refresh scheduler
- Patent number 6,954,387
- Issue date Oct 11, 2005
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Cell data margin test with dummy cell
- Patent number 6,950,353
- Issue date Sep 27, 2005
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Gain cell memory having read cycle interlock
- Patent number 6,947,348
- Issue date Sep 20, 2005
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Bi-directional read write data structure and method for memory
- Patent number 6,816,397
- Issue date Nov 9, 2004
- International Business Machines Corporation
- John W. Golz
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure and method of making three finger folded field effect tra...
- Patent number 6,768,143
- Issue date Jul 27, 2004
- International Business Machines Corporation
- Gregory J. Fredeman
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY CIRCUIT, DESIGN STRUCTURE AND METHOD
- Publication number 20090268510
- Publication date Oct 29, 2009
- John E. Barth, JR.
- G11 - INFORMATION STORAGE
Information Patent Application
FLOATING BODY CONTROL IN SOI DRAM
- Publication number 20090154258
- Publication date Jun 18, 2009
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Three Dimensional Twisted Bitline Architecture for Multi-port Memory
- Publication number 20090103390
- Publication date Apr 23, 2009
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRICAL ANTIFUSE WITH INTEGRATED SENSOR
- Publication number 20080217658
- Publication date Sep 11, 2008
- International Business Machines Corporation
- Deok-kee Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH AN ASYMMETRI...
- Publication number 20080150026
- Publication date Jun 26, 2008
- International Business Machines Corporation
- Oh-Jung Kwon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLOATING BODY CONTROL IN SOI DRAM
- Publication number 20080084774
- Publication date Apr 10, 2008
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE CYCLE REFRESH OF MULTI-PORT DYNAMIC RANDOM ACCESS MEMORY (DRAM)
- Publication number 20060285411
- Publication date Dec 21, 2006
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Three Dimensional Twisted Bitline Architecture for Multi-Port Memory
- Publication number 20060285420
- Publication date Dec 21, 2006
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER MANAGER FOR STANDBY OPERATION OF A MEMORY SYSTEM
- Publication number 20060039226
- Publication date Feb 23, 2006
- David R. Hanson
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-PORT MEMORY ARCHITECTURE
- Publication number 20050047218
- Publication date Mar 3, 2005
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Application
GAIN CELL MEMORY HAVING READ CYCLE INTERLOCK
- Publication number 20050024923
- Publication date Feb 3, 2005
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY WITH SMART REFRESH SCHEDULER
- Publication number 20050013185
- Publication date Jan 20, 2005
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Low power manager for standby operation
- Publication number 20040252573
- Publication date Dec 16, 2004
- International Business Machine Corporation
- David R. Hanson
- G11 - INFORMATION STORAGE
Information Patent Application
BI-DIRECTIONAL READ WRITE DATA STRUCTURE AND METHOD FOR MEMORY
- Publication number 20040240246
- Publication date Dec 2, 2004
- John W. Golz
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Three dimensional twisted bitline architecture for multi-port memory

Electrical antifuse with integrated sensor

Dynamic random access memory circuit, design structure and method

Floating body control in SOI DRAM

Floating body control in SOI DRAM

Three dimensional twisted bitline architecture for multi-port memory

Single cycle refresh of multi-port dynamic random access memory (DRAM)

DRAM with self-resetting data path for reduced power consumption

Bi-mode sense amplifier with dual utilization of the reference cell...

Low power manager for standby operation of memory system

Low power manager for standby operation of a memory system

Multi-port memory architecture

Dynamic random access memory with smart refresh scheduler

Cell data margin test with dummy cell

Gain cell memory having read cycle interlock

Bi-directional read write data structure and method for memory

Structure and method of making three finger folded field effect tra...

Patents Applicationslast 30 patents

DYNAMIC RANDOM ACCESS MEMORY CIRCUIT, DESIGN STRUCTURE AND METHOD

FLOATING BODY CONTROL IN SOI DRAM

Three Dimensional Twisted Bitline Architecture for Multi-port Memory

ELECTRICAL ANTIFUSE WITH INTEGRATED SENSOR

METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH AN ASYMMETRI...

FLOATING BODY CONTROL IN SOI DRAM

SINGLE CYCLE REFRESH OF MULTI-PORT DYNAMIC RANDOM ACCESS MEMORY (DRAM)

Three Dimensional Twisted Bitline Architecture for Multi-Port Memory

LOW POWER MANAGER FOR STANDBY OPERATION OF A MEMORY SYSTEM

MULTI-PORT MEMORY ARCHITECTURE

GAIN CELL MEMORY HAVING READ CYCLE INTERLOCK

DYNAMIC RANDOM ACCESS MEMORY WITH SMART REFRESH SCHEDULER

Low power manager for standby operation

BI-DIRECTIONAL READ WRITE DATA STRUCTURE AND METHOD FOR MEMORY