Holger Wetter

Person

Weil im Schoenbuch, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Layouting of interconnect lines in integrated circuits
- Patent number 10,013,521
- Issue date Jul 3, 2018
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling an incremental sign-off process using design data
- Patent number 9,922,154
- Issue date Mar 20, 2018
- International Business Machines Corporation
- Hans-Werner Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write-bitline control in multicore SRAM arrays
- Patent number 9,761,304
- Issue date Sep 12, 2017
- International Business Machines Corporation
- Joachim Keinert
- G11 - INFORMATION STORAGE
Information Patent Grant
Incorporating synthesized netlists as subcomponents in a hierarchic...
- Patent number 8,560,983
- Issue date Oct 15, 2013
- International Business Machines Corporation
- Uwe Brandt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shifter with all-one and all-zero detection using a portion of part...
- Patent number 8,332,453
- Issue date Dec 11, 2012
- International Business Machines Corporation
- Maarten Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast routing of custom macros
- Patent number 8,286,115
- Issue date Oct 9, 2012
- International Business Machines Corporation
- Holger Wetter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for scanning sequential logic elements
- Patent number 7,913,132
- Issue date Mar 22, 2011
- International Business Machines Corporation
- Tobias Gemmeke
- G01 - MEASURING TESTING
Information Patent Grant
Method for calculating a result of a division with a floating point...
- Patent number 7,873,687
- Issue date Jan 18, 2011
- International Business Machines Corporation
- Guenter Gerwig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary and decimal adder unit
- Patent number 6,292,819
- Issue date Sep 18, 2001
- International Business Machines Corporation
- Wolfgang Bultmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined adder and logic unit
- Patent number 5,944,772
- Issue date Aug 31, 1999
- International Business Machines Corporation
- Juergen Haas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined binary/decimal adder unit
- Patent number 5,928,319
- Issue date Jul 27, 1999
- International Business Machines Corporation
- Wilhelm Haller
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20180285514
- Publication date Oct 4, 2018
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20180285513
- Publication date Oct 4, 2018
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING AN INCREMENTAL SIGN-OFF PROCESS USING DESIGN DATA
- Publication number 20170337314
- Publication date Nov 23, 2017
- International Business Machines Corporation
- Hans-Werner Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20170140088
- Publication date May 18, 2017
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Incorporating Synthesized Netlists as Subcomponents in a Hierarchic...
- Publication number 20130145329
- Publication date Jun 6, 2013
- International Business Machines Corporation
- Uwe Brandt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHIFTER WITH ALL-ONE AND ALL-ZERO DETECTION
- Publication number 20100146023
- Publication date Jun 10, 2010
- International Business Machines Corporation
- Maarten Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST ROUTING OF CUSTOM MACROS
- Publication number 20100146471
- Publication date Jun 10, 2010
- International Business Machines Corporation
- Holger Wetter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Scanning Sequential Logic Elements
- Publication number 20090135961
- Publication date May 28, 2009
- International Business Machines Corporation
- Tobias Gemmeke
- G01 - MEASURING TESTING
Information Patent Application
Method for Calculating a Result of a Division with a Floating Point...
- Publication number 20070083583
- Publication date Apr 12, 2007
- Guenter Gerwig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Highly parallel structure for fast multi cycle binary and decimal a...
- Publication number 20060031279
- Publication date Feb 9, 2006
- International Business Machines Corporation
- Wilhelm Haller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fast integer division with minimum number of iterations in substrac...
- Publication number 20040249877
- Publication date Dec 9, 2004
- International Business Machines Corporation
- Guenter Gerwig
- G06 - COMPUTING CALCULATING COUNTING

Holger Wetter

Person

Patents Grantslast 30 patents

Layouting of interconnect lines in integrated circuits

Enabling an incremental sign-off process using design data

Write-bitline control in multicore SRAM arrays

Incorporating synthesized netlists as subcomponents in a hierarchic...

Shifter with all-one and all-zero detection using a portion of part...

Fast routing of custom macros

System and method for scanning sequential logic elements

Method for calculating a result of a division with a floating point...

Binary and decimal adder unit

Combined adder and logic unit

Combined binary/decimal adder unit

Patents Applicationslast 30 patents

LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

ENABLING AN INCREMENTAL SIGN-OFF PROCESS USING DESIGN DATA

LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

Incorporating Synthesized Netlists as Subcomponents in a Hierarchic...

SHIFTER WITH ALL-ONE AND ALL-ZERO DETECTION

FAST ROUTING OF CUSTOM MACROS

System and Method for Scanning Sequential Logic Elements

Method for Calculating a Result of a Division with a Floating Point...

Highly parallel structure for fast multi cycle binary and decimal a...

Fast integer division with minimum number of iterations in substrac...