Hong Shi

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Chip package with near-die integrated passive device
- Patent number 12,136,613
- Issue date Nov 5, 2024
- Xilinx, Inc.
- Li-Sheng Weng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In-package passive inductive element for reflection mitigation
- Patent number 11,735,519
- Issue date Aug 22, 2023
- Xilinx, Inc.
- Zhaoyin Daniel Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Core cavity noise isolation structure for use in chip packages
- Patent number 11,688,675
- Issue date Jun 27, 2023
- Xilinx, Inc.
- Frank Peter Lambrecht
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modular stacked silicon package assembly
- Patent number 11,302,674
- Issue date Apr 12, 2022
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus of package enabled ESD protection
- Patent number 11,043,484
- Issue date Jun 22, 2021
- Xilinx, Inc.
- Hong Shi
- G01 - MEASURING TESTING
Information Patent Grant
Chip scale package (CSP) including shim die
- Patent number 10,770,364
- Issue date Sep 8, 2020
- Xilinx, Inc.
- Hong Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low crosstalk vertical connection interface
- Patent number 10,314,163
- Issue date Jun 4, 2019
- Xilinx, Inc.
- Hong Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power-ground co-reference transceiver structure to deliver ultra-lo...
- Patent number 10,057,976
- Issue date Aug 21, 2018
- Xilinx, Inc.
- Hong Shi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power distribution network
- Patent number 9,536,820
- Issue date Jan 3, 2017
- Altera Corporation
- Hui Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package routing with reduced crosstalk
- Patent number 9,425,149
- Issue date Aug 23, 2016
- Altera Corporation
- Xiaohong Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC package with non-uniform dielectric layer thickness
- Patent number 9,401,330
- Issue date Jul 26, 2016
- Altera Corporation
- Xiaohong Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tunable power distribution network and method of use thereof
- Patent number 9,331,014
- Issue date May 3, 2016
- Altera Corporation
- Hui Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with reduced pad capacitance
- Patent number 9,245,835
- Issue date Jan 26, 2016
- Altera Corporation
- Xiaohong Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adjustable drive strength input-output buffer circuitry
- Patent number 9,099,999
- Issue date Aug 4, 2015
- Altera Corporation
- Bonnie I. Wang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Techniques for attenuating resonance induced impedance in integrate...
- Patent number 9,078,354
- Issue date Jul 7, 2015
- Altera Corporation
- Hong Shi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods and apparatus for transceiver power noise reduction
- Patent number 8,923,417
- Issue date Dec 30, 2014
- Altera Corporation
- Zhe Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High performance PCB
- Patent number 8,841,561
- Issue date Sep 23, 2014
- Altera Corporation
- Xiaohong Jiang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Compensation network using an on-die compensation inductor
- Patent number 8,723,293
- Issue date May 13, 2014
- Altera Corporation
- Xiaohong Jiang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Tunable power distribution network and method of use thereof
- Patent number 8,716,898
- Issue date May 6, 2014
- Altera Corporation
- Hui Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically tapered transmission line for optimal signal transition...
- Patent number 8,502,386
- Issue date Aug 6, 2013
- Altera Corporation
- Xiaohong Jiang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Power distribution network
- Patent number 8,498,129
- Issue date Jul 30, 2013
- Altera Corporation
- Hui Liu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Compensation network using an on-die compensation inductor
- Patent number 8,368,174
- Issue date Feb 5, 2013
- Altera Corporation
- Xiaohong Jiang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interconnect pattern for transceiver package
- Patent number 8,294,259
- Issue date Oct 23, 2012
- Altera Corporation
- Xiaohong Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for attenuating resonance induced impedance in integrate...
- Patent number 8,164,916
- Issue date Apr 24, 2012
- Altera Corportation
- Hong Shi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Simultaneous switching noise filter architecture and method
- Patent number 7,990,235
- Issue date Aug 2, 2011
- Altera Corporation
- Yee Huan Yew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Return loss techniques in wirebond packages for high-speed data com...
- Patent number 7,825,527
- Issue date Nov 2, 2010
- Altera Corporation
- William W. Bereza
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically tapered transmission line for optimal signal transition...
- Patent number 7,752,587
- Issue date Jul 6, 2010
- Altera Corporation
- Xiaohong Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Substrate via patterns for optimal power distribution and manufactu...
- Patent number 7,640,523
- Issue date Dec 29, 2009
- Altera Corporation
- Hong Shi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
BGA package with wiring schemes having reduced current loop paths t...
- Patent number 7,501,709
- Issue date Mar 10, 2009
- Altera Corporation
- Vincent Hool
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of optimizing interconnect distribution to improve signal in...
- Patent number 7,472,367
- Issue date Dec 30, 2008
- Altera Corporation
- Yuanlin Xie
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CHIP PACKAGE WITH INTEGRATED EMBEDDED OFF-DIE INDUCTORS
- Publication number 20240071958
- Publication date Feb 29, 2024
- Xilinx, Inc.
- Hong SHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COUPLED LOOP AND VOID STRUCTURE INTEGRATED IN A REDISTRIBUTION LAYE...
- Publication number 20230335510
- Publication date Oct 19, 2023
- Xilinx, Inc.
- Po-Wei CHIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE WITH NEAR-DIE INTEGRATED PASSIVE DEVICE
- Publication number 20230253380
- Publication date Aug 10, 2023
- Xilinx, Inc.
- Li-Sheng WENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IN-PACKAGE PASSIVE INDUCTIVE ELEMENT FOR REFLECTION MITIGATION
- Publication number 20220415788
- Publication date Dec 29, 2022
- Xilinx, Inc.
- Zhaoyin Daniel WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MODULAR STACKED SILICON PACKAGE ASSEMBLY
- Publication number 20210366873
- Publication date Nov 25, 2021
- Xilinx, Inc.
- Jaspreet Singh GANDHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP SCALE PACKAGE (CSP) INCLUDING SHIM DIE
- Publication number 20190318975
- Publication date Oct 17, 2019
- Xilinx, Inc.
- Hong Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW CROSSTALK VERTICAL CONNECTION INTERFACE
- Publication number 20180338375
- Publication date Nov 22, 2018
- Xilinx, Inc.
- Hong Shi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
THIN PROFILE METAL TRACE TO SUPPRESS SKIN EFFECT AND EXTEND PACKAGE...
- Publication number 20150282299
- Publication date Oct 1, 2015
- Xilinx, Inc.
- Hong Shi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Integrated Circuits With On-Die Decoupling Capacitors
- Publication number 20140374877
- Publication date Dec 25, 2014
- Altera Corporation
- Kyung Suk Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS FOR ELECTRONIC ASSEMBLY WITH IMPROVED INTERCONNECT AND AS...
- Publication number 20140264783
- Publication date Sep 18, 2014
- Altera Corporation
- Hui Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT PATTERN FOR TRANSCEIVER PACKAGE
- Publication number 20110193233
- Publication date Aug 11, 2011
- Xiaohong Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Vertically Tapered Transmission Line for Optimal Signal Transition...
- Publication number 20100148375
- Publication date Jun 17, 2010
- Xiaohong Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETURN LOSS TECHNIQUES IN WIREBOND PACKAGES FOR HIGH-SPEED DATA COM...
- Publication number 20090309240
- Publication date Dec 17, 2009
- William W. Bereza
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICALLY TAPERED TRANSMISSION LINE FOR OPTIMAL SIGNAL TRANSITION...
- Publication number 20090077523
- Publication date Mar 19, 2009
- Xiaohong Jiang
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Chip package with near-die integrated passive device

In-package passive inductive element for reflection mitigation

Core cavity noise isolation structure for use in chip packages

Modular stacked silicon package assembly

Method and apparatus of package enabled ESD protection

Chip scale package (CSP) including shim die

Low crosstalk vertical connection interface

Power-ground co-reference transceiver structure to deliver ultra-lo...

Power distribution network

Integrated circuit package routing with reduced crosstalk

IC package with non-uniform dielectric layer thickness

Tunable power distribution network and method of use thereof

Integrated circuit package with reduced pad capacitance

Adjustable drive strength input-output buffer circuitry

Techniques for attenuating resonance induced impedance in integrate...

Methods and apparatus for transceiver power noise reduction

High performance PCB

Compensation network using an on-die compensation inductor

Tunable power distribution network and method of use thereof

Vertically tapered transmission line for optimal signal transition...

Power distribution network

Compensation network using an on-die compensation inductor

Interconnect pattern for transceiver package

Techniques for attenuating resonance induced impedance in integrate...

Simultaneous switching noise filter architecture and method

Return loss techniques in wirebond packages for high-speed data com...

Vertically tapered transmission line for optimal signal transition...

Substrate via patterns for optimal power distribution and manufactu...

BGA package with wiring schemes having reduced current loop paths t...

Method of optimizing interconnect distribution to improve signal in...

Patents Applicationslast 30 patents

CHIP PACKAGE WITH INTEGRATED EMBEDDED OFF-DIE INDUCTORS

COUPLED LOOP AND VOID STRUCTURE INTEGRATED IN A REDISTRIBUTION LAYE...

CHIP PACKAGE WITH NEAR-DIE INTEGRATED PASSIVE DEVICE

IN-PACKAGE PASSIVE INDUCTIVE ELEMENT FOR REFLECTION MITIGATION

MODULAR STACKED SILICON PACKAGE ASSEMBLY

CHIP SCALE PACKAGE (CSP) INCLUDING SHIM DIE

LOW CROSSTALK VERTICAL CONNECTION INTERFACE

THIN PROFILE METAL TRACE TO SUPPRESS SKIN EFFECT AND EXTEND PACKAGE...

Integrated Circuits With On-Die Decoupling Capacitors

APPARATUS FOR ELECTRONIC ASSEMBLY WITH IMPROVED INTERCONNECT AND AS...

INTERCONNECT PATTERN FOR TRANSCEIVER PACKAGE

Vertically Tapered Transmission Line for Optimal Signal Transition...

RETURN LOSS TECHNIQUES IN WIREBOND PACKAGES FOR HIGH-SPEED DATA COM...

VERTICALLY TAPERED TRANSMISSION LINE FOR OPTIMAL SIGNAL TRANSITION...