Howard G. Sachs

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit group design methodologies
- Patent number 7,234,123
- Issue date Jun 19, 2007
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for repair of ROM programming errors or defects
- Patent number 7,103,736
- Issue date Sep 5, 2006
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Idle power reduction for state machines
- Patent number 7,058,832
- Issue date Jun 6, 2006
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G05 - CONTROLLING REGULATING
Information Patent Grant
Instruction cache association crossbar switch
- Patent number 7,039,791
- Issue date May 2, 2006
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit group design methodologies
- Patent number 6,910,199
- Issue date Jun 21, 2005
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
VLIW processor and method therefor
- Patent number 6,892,293
- Issue date May 10, 2005
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction cache associative crossbar switch
- Patent number 6,360,313
- Issue date Mar 19, 2002
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling an instruction pipeline in a d...
- Patent number 6,282,635
- Issue date Aug 28, 2001
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling an instruction pipeline in a d...
- Patent number 5,996,062
- Issue date Nov 30, 1999
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction cache associative crossbar switch system
- Patent number 5,794,003
- Issue date Aug 11, 1998
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software scheduled superscalar computer architecture
- Patent number 5,560,028
- Issue date Sep 24, 1996
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for obtaining data from a translation memory based on car...
- Patent number 5,502,829
- Issue date Mar 26, 1996
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for translating virtual addresses in a data pr...
- Patent number 5,463,750
- Issue date Oct 31, 1995
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory address translation system having modifiable and non-modifia...
- Patent number 5,255,384
- Issue date Oct 19, 1993
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache providing caching/non-caching write-through and copyback mode...
- Patent number 5,091,846
- Issue date Feb 25, 1992
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for maintaining consistency of a cache memory with a prim...
- Patent number 4,933,835
- Issue date Jun 12, 1990
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache-MMU system
- Patent number 4,899,275
- Issue date Feb 6, 1990
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for addressing a cache memory
- Patent number 4,884,197
- Issue date Nov 28, 1989
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quadword boundary cache system
- Patent number 4,860,192
- Issue date Aug 22, 1989
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Minimized Table Lookup
- Publication number 20080186316
- Publication date Aug 7, 2008
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Convolver Architecture for Vector Processor
- Publication number 20080059757
- Publication date Mar 6, 2008
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instructions for Vector Processor
- Publication number 20080059760
- Publication date Mar 6, 2008
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory architecture for vector processor
- Publication number 20080059758
- Publication date Mar 6, 2008
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Vector Processor Architecture
- Publication number 20080059759
- Publication date Mar 6, 2008
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Pipe Vector Block Matching Operations
- Publication number 20080052489
- Publication date Feb 28, 2008
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Vector processor with multi-pipe vector block matching
- Publication number 20070150697
- Publication date Jun 28, 2007
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Vector processor with special purpose registers and high speed memo...
- Publication number 20060259737
- Publication date Nov 16, 2006
- Telairity Semiconductor, Inc.
- Howard Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for clock synchronization between a processor...
- Publication number 20060259807
- Publication date Nov 16, 2006
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Direct memory access (DMA) method and apparatus and DMA for video p...
- Publication number 20060259657
- Publication date Nov 16, 2006
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for repair of ROM programming errors or defects
- Publication number 20050039071
- Publication date Feb 17, 2005
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit group design methodologies
- Publication number 20050028128
- Publication date Feb 3, 2005
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit group design methodologies
- Publication number 20050022146
- Publication date Jan 27, 2005
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION CACHE ASSOCIATIVE CROSSBAR SWITCH
- Publication number 20030191923
- Publication date Oct 9, 2003
- HOWARD G. SACHS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
General purpose state machine
- Publication number 20030140218
- Publication date Jul 24, 2003
- Teleraty Systems, Inc.
- Howard G. Sachs
- G05 - CONTROLLING REGULATING
Information Patent Application
Idle power reduction for state machines
- Publication number 20030140219
- Publication date Jul 24, 2003
- Telairity Semiconductor, Inc.
- Howard G. Sachs
- G05 - CONTROLLING REGULATING
Information Patent Application
Instruction cache association crossbar switch
- Publication number 20030079112
- Publication date Apr 24, 2003
- Intergraph Corporation
- Howard G. Sachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit group design methodologies
- Publication number 20020184600
- Publication date Dec 5, 2002
- Howard Sachs
- G06 - COMPUTING CALCULATING COUNTING

Howard G. Sachs

Person

Patents Grantslast 30 patents

Circuit group design methodologies

System for repair of ROM programming errors or defects

Idle power reduction for state machines

Instruction cache association crossbar switch

Circuit group design methodologies

VLIW processor and method therefor

Instruction cache associative crossbar switch

Method and apparatus for controlling an instruction pipeline in a d...

Method and apparatus for controlling an instruction pipeline in a d...

Instruction cache associative crossbar switch system

Software scheduled superscalar computer architecture

Apparatus for obtaining data from a translation memory based on car...

Method and apparatus for translating virtual addresses in a data pr...

Memory address translation system having modifiable and non-modifia...

Cache providing caching/non-caching write-through and copyback mode...

Apparatus for maintaining consistency of a cache memory with a prim...

Cache-MMU system

Method and apparatus for addressing a cache memory

Quadword boundary cache system

Patents Applicationslast 30 patents

Minimized Table Lookup

Convolver Architecture for Vector Processor

Instructions for Vector Processor

Memory architecture for vector processor

Vector Processor Architecture

Multi-Pipe Vector Block Matching Operations

Vector processor with multi-pipe vector block matching

Vector processor with special purpose registers and high speed memo...

Method and apparatus for clock synchronization between a processor...

Direct memory access (DMA) method and apparatus and DMA for video p...

System for repair of ROM programming errors or defects

Circuit group design methodologies

Circuit group design methodologies

INSTRUCTION CACHE ASSOCIATIVE CROSSBAR SWITCH

General purpose state machine

Idle power reduction for state machines

Instruction cache association crossbar switch

Circuit group design methodologies