Howard K. Kalter

Person

Colchester, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for chip testing
- Patent number 6,730,529
- Issue date May 4, 2004
- International Business Machines Corporation
- Howard L. Kalter
- G01 - MEASURING TESTING
Information Patent Grant
Structure for folded architecture pillar memory cell
- Patent number 6,440,801
- Issue date Aug 27, 2002
- International Business Machines Corporation
- Toshiharu Furukawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-level dram trench store utilizing two capacitors and two plates
- Patent number 6,429,080
- Issue date Aug 6, 2002
- International Business Machines Corporation
- Toshiharu Furukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Structures for wafer level test and burn-in
- Patent number 6,426,904
- Issue date Jul 30, 2002
- International Business Machines Corporation
- John E. Barth
- G01 - MEASURING TESTING
Information Patent Grant
Voltage controlled transmission line with real-time adaptive control
- Patent number 6,369,671
- Issue date Apr 9, 2002
- International Business Machines Corporation
- Claude L. Bertin
- G11 - INFORMATION STORAGE
Information Patent Grant
Interconnected integrated circuits having reduced inductance during...
- Patent number 6,345,380
- Issue date Feb 5, 2002
- International Business Machines Corporation
- Anthony R. Bonaccio
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of forming self-isolated and self-aligned 4F-square vertical...
- Patent number 6,316,309
- Issue date Nov 13, 2001
- Steven John Holmes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for providing self-terminating signal lines
- Patent number 6,294,942
- Issue date Sep 25, 2001
- International Business Machines Corporation
- Claude L. Bertin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-level DRAM trench store utilizing two capacitors and two plates
- Patent number 6,282,115
- Issue date Aug 28, 2001
- International Business Machines Corporation
- Toshiharu Furukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for increasing interchip communications rates
- Patent number 6,255,899
- Issue date Jul 3, 2001
- International Business Machines Corporation
- Claude L. Bertin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structures for wafer level test and burn-in
- Patent number 6,233,184
- Issue date May 15, 2001
- International Business Machines Corporation
- John E. Barth
- G01 - MEASURING TESTING
Information Patent Grant
Redundant input/output driver circuit
- Patent number 6,177,809
- Issue date Jan 23, 2001
- International Business Machines Corporation
- William R. Tonti
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Complementary depletion switch body stack off-chip driver
- Patent number 6,177,818
- Issue date Jan 23, 2001
- International Business Machines Corporation
- Claude L. Bertin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-isolated and self-aligned 4F-square vertical fet-trench dram c...
- Patent number 6,137,128
- Issue date Oct 24, 2000
- International Business Machines Corporation
- Steven John Holmes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for folded architecture pillar memory cell
- Patent number 6,114,725
- Issue date Sep 5, 2000
- International Business Machines Corporation
- Toshiharu Furukawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a very dense chip package
- Patent number 6,087,199
- Issue date Jul 11, 2000
- International Business Machines Corporation
- H. Bernhard Pogge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned diffused source vertical transistors with stack capaci...
- Patent number 6,077,745
- Issue date Jun 20, 2000
- International Business Machines Corporation
- Stuart Mcallister Burns
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interactive method for self-adjusted access on embedded DRAM memory...
- Patent number 6,044,024
- Issue date Mar 28, 2000
- International Business Machines Corporation
- John E. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-aligned diffused source vertical transistors with deep trench...
- Patent number 6,034,389
- Issue date Mar 7, 2000
- International Business Machines Corporation
- Stuart Mcallister Burns
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned diffused source vertical transistors with deep trench...
- Patent number 6,013,548
- Issue date Jan 11, 2000
- International Business Machines Corporation
- Stuart Mcallister Burns
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Very dense chip package
- Patent number 5,998,868
- Issue date Dec 7, 1999
- International Business Machines Corporation
- H. Bernhard Pogge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method or forming self-aligned halo-isolated wells
- Patent number 5,972,745
- Issue date Oct 26, 1999
- International Business Machines Corporation
- Howard L. Kalter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Processor based BIST for an embedded memory
- Patent number 5,961,653
- Issue date Oct 5, 1999
- International Business Machines Corporation
- Howard Leo Kalter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-aligned diffused source vertical transistors with stack capaci...
- Patent number 5,929,477
- Issue date Jul 27, 1999
- International Business Machines Corporation
- Stuart McAllister Burns
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for precise definition of integrated circuit chip edges
- Patent number 5,925,924
- Issue date Jul 20, 1999
- International Business Machines Corporation
- John Edward Cronin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for chip testing
- Patent number 5,899,703
- Issue date May 4, 1999
- International Business Machines Corporation
- Howard L. Kalter
- G01 - MEASURING TESTING
Information Patent Grant
Multi-port multiple-simultaneous-access DRAM chip
- Patent number 5,875,470
- Issue date Feb 23, 1999
- International Business Machines Corporation
- Jeffrey Harris Dreibelbis
- G11 - INFORMATION STORAGE
Information Patent Grant
Very dense integrated circuit package and method for forming the same
- Patent number 5,866,443
- Issue date Feb 2, 1999
- International Business Machines Corporation
- H. Bernhard Pogge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Very dense integrated circuit package
- Patent number 5,814,885
- Issue date Sep 29, 1998
- International Business Machines Corporation
- H. Bernhard Pogge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit chip with a wide I/O memory array and redundant...
- Patent number 5,796,662
- Issue date Aug 18, 1998
- International Business Machines Corporation
- Howard Leo Kalter
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Structures for wafer level test and burn -in
- Publication number 20010046168
- Publication date Nov 29, 2001
- John E. Barth
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR PROVIDING SELF-TERMINATING SIGNAL LINES
- Publication number 20010013803
- Publication date Aug 16, 2001
- CLAUDE L. BERTIN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multi-level dram trench store utilizing two capacitors and two plates
- Publication number 20010012215
- Publication date Aug 9, 2001
- Toshiharu Furukawa
- H01 - BASIC ELECTRIC ELEMENTS

Howard K. Kalter

Person

Patents Grantslast 30 patents

Method for chip testing

Structure for folded architecture pillar memory cell

Multi-level dram trench store utilizing two capacitors and two plates

Structures for wafer level test and burn-in

Voltage controlled transmission line with real-time adaptive control

Interconnected integrated circuits having reduced inductance during...

Method of forming self-isolated and self-aligned 4F-square vertical...

Method and apparatus for providing self-terminating signal lines

Multi-level DRAM trench store utilizing two capacitors and two plates

Method and apparatus for increasing interchip communications rates

Structures for wafer level test and burn-in

Redundant input/output driver circuit

Complementary depletion switch body stack off-chip driver

Self-isolated and self-aligned 4F-square vertical fet-trench dram c...

Structure for folded architecture pillar memory cell

Method for fabricating a very dense chip package

Self-aligned diffused source vertical transistors with stack capaci...

Interactive method for self-adjusted access on embedded DRAM memory...

Self-aligned diffused source vertical transistors with deep trench...

Self-aligned diffused source vertical transistors with deep trench...

Very dense chip package

Method or forming self-aligned halo-isolated wells

Processor based BIST for an embedded memory

Self-aligned diffused source vertical transistors with stack capaci...

Methods for precise definition of integrated circuit chip edges

Method for chip testing

Multi-port multiple-simultaneous-access DRAM chip

Very dense integrated circuit package and method for forming the same

Very dense integrated circuit package

Integrated circuit chip with a wide I/O memory array and redundant...

Patents Applicationslast 30 patents

Structures for wafer level test and burn -in

METHOD AND APPARATUS FOR PROVIDING SELF-TERMINATING SIGNAL LINES

Multi-level dram trench store utilizing two capacitors and two plates