Howard S. David

Person

Porland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stuffing bits on a memory bus between data bursts
- Patent number 9,448,956
- Issue date Sep 20, 2016
- Intel Corporation
- William Dawson Kesling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to limit memory power
- Patent number 8,738,937
- Issue date May 27, 2014
- Intel Corporation
- Howard S. David
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and system to improve the operations of a registered memory...
- Patent number 8,661,284
- Issue date Feb 25, 2014
- Intel Corporation
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory power management via dynamic memory operation states
- Patent number 8,438,410
- Issue date May 7, 2013
- Intel Corporation
- Howard S. David
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Memory power estimation by means of calibrated weights and activity...
- Patent number 8,412,479
- Issue date Apr 2, 2013
- Intel Corporation
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system to improve the operations of a registered memory...
- Patent number 8,375,241
- Issue date Feb 12, 2013
- Intel Corporation
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive memory frequency scaling
- Patent number 8,327,172
- Issue date Dec 4, 2012
- Intel Corporation
- Howard S. David
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Power management using adaptive thermal throttling
- Patent number 8,122,265
- Issue date Feb 21, 2012
- Intel Corporation
- Sivakumar Radhakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory rank burst scheduling
- Patent number 8,046,559
- Issue date Oct 25, 2011
- Intel Corporation
- Hongzhong Zheng
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Coarsely controlling memory power states
- Patent number 7,958,380
- Issue date Jun 7, 2011
- Intel Corporation
- Sandeep K. Jain
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Multiple address outputs for programming the memory register set di...
- Patent number 7,864,604
- Issue date Jan 4, 2011
- Intel Corporation
- Howard S. David
- G11 - INFORMATION STORAGE
Information Patent Grant
Temperature sampling in electronic devices
- Patent number 7,844,876
- Issue date Nov 30, 2010
- Intel Corporation
- David Wyatt
- G01 - MEASURING TESTING
Information Patent Grant
System and method for memory phase shedding
- Patent number 7,804,733
- Issue date Sep 28, 2010
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing mode register set commands
- Patent number 7,626,884
- Issue date Dec 1, 2009
- Intel Corporation
- Christopher Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Partial bank DRAM precharge
- Patent number 7,392,339
- Issue date Jun 24, 2008
- Intel Corporation
- Howard S. David
- G11 - INFORMATION STORAGE
Information Patent Grant
Distributed memory module cache writeback
- Patent number 7,389,387
- Issue date Jun 17, 2008
- Intel Corporation
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for thermal throttling of memory modules
- Patent number 7,318,130
- Issue date Jan 8, 2008
- Intel Corporation
- Warren R. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ballout for buffer
- Patent number 7,269,025
- Issue date Sep 11, 2007
- Intel Corporation
- Howard David
- G11 - INFORMATION STORAGE
Information Patent Grant
Side-by-side inverted memory address and command buses
- Patent number 7,188,208
- Issue date Mar 6, 2007
- Intel Corporation
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two dimensional data eye centering for source synchronous data tran...
- Patent number 7,036,053
- Issue date Apr 25, 2006
- Intel Corporation
- John F. Zumkehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method to track flag transitions for DRAM data transfer
- Patent number 6,976,120
- Issue date Dec 13, 2005
- Intel Corporation
- Narendra S. Khandekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to track command signal occurrence for DRAM da...
- Patent number 6,976,121
- Issue date Dec 13, 2005
- Intel Corporation
- Narendra S. Khandekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed memory module cache
- Patent number 6,938,129
- Issue date Aug 30, 2005
- Intel Corporation
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed memory module cache command formatting
- Patent number 6,931,505
- Issue date Aug 16, 2005
- Intel Corporation
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed memory module cache prefetch
- Patent number 6,925,534
- Issue date Aug 2, 2005
- Intel Corporation
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed memory module cache tag look-up
- Patent number 6,880,044
- Issue date Apr 12, 2005
- Intel Corporation
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Segmented distributed memory module cache
- Patent number 6,865,646
- Issue date Mar 8, 2005
- Intel Corporation
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of addressing individual memory devices on a memory module
- Patent number 6,832,177
- Issue date Dec 14, 2004
- Intel Corporation
- Narendra S. Khandekar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system with burst length shorter than prefetch length
- Patent number 6,795,899
- Issue date Sep 21, 2004
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for sequencing system bus grants and disabling...
- Patent number 6,026,460
- Issue date Feb 15, 2000
- Intel Corporation
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIERARCHICAL AND PARALLEL PARTITION NETWORKS
- Publication number 20150178092
- Publication date Jun 25, 2015
- Asit K. MISHRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINE CODING FOR LOW-RADIO NOISE MEMORY INTERFACES
- Publication number 20140156902
- Publication date Jun 5, 2014
- William Dawson Kesling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM TO IMPROVE THE OPERATIONS OF A REGISTERED MEMORY...
- Publication number 20130145197
- Publication date Jun 6, 2013
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO LIMIT MEMORY POWER
- Publication number 20120017099
- Publication date Jan 19, 2012
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY POWER ESTIMATION BY MEANS OF CALIBRATED WEIGHTS AND ACTIVITY...
- Publication number 20110320150
- Publication date Dec 29, 2011
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY POWER MANAGEMENT VIA DYNAMIC MEMORY OPERATION STATES
- Publication number 20110320839
- Publication date Dec 29, 2011
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE MEMORY FREQUENCY SCALING
- Publication number 20110320846
- Publication date Dec 29, 2011
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM TO IMPROVE THE OPERATIONS OF A REGISTERED MEMORY...
- Publication number 20100257398
- Publication date Oct 7, 2010
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY RANK BURST SCHEDULING
- Publication number 20090248994
- Publication date Oct 1, 2009
- Hongzhong Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MEMORY PHASE SHEDDING
- Publication number 20090172442
- Publication date Jul 2, 2009
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing mode register set commands
- Publication number 20090109771
- Publication date Apr 30, 2009
- Christopher Cox
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE ADDRESS OUTPUTS FOR PROGRAMMING THE MEMORY REGISTER SET DI...
- Publication number 20090085604
- Publication date Apr 2, 2009
- Howard S. David
- G11 - INFORMATION STORAGE
Information Patent Application
Coarsely controlling memory power states
- Publication number 20080294928
- Publication date Nov 27, 2008
- Sandeep K. Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power management using adaptive thermal throttling
- Publication number 20080163226
- Publication date Jul 3, 2008
- Intel Corporation
- Sivakumar Radhakrisnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Temperature sampling in electronic devices
- Publication number 20080040408
- Publication date Feb 14, 2008
- David Wyatt
- G01 - MEASURING TESTING
Information Patent Application
Temperature sampling in electronic devices
- Publication number 20080039981
- Publication date Feb 14, 2008
- David Wyatt
- G01 - MEASURING TESTING
Information Patent Application
Ballout for buffer
- Publication number 20060146509
- Publication date Jul 6, 2006
- Howard David
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Side-by-side inverted memory address and command buses
- Publication number 20060053243
- Publication date Mar 9, 2006
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for thermal throttling of memory modules
- Publication number 20050289292
- Publication date Dec 29, 2005
- Warren R. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partial bank DRAM precharge
- Publication number 20050132131
- Publication date Jun 16, 2005
- Intel Corporation
- Howard S. David
- G11 - INFORMATION STORAGE
Information Patent Application
Partial bank DRAM refresh
- Publication number 20050108460
- Publication date May 19, 2005
- Intel Corporation
- Howard S. David
- G11 - INFORMATION STORAGE
Information Patent Application
Method of addressing individual memory devices on a memory module
- Publication number 20040128429
- Publication date Jul 1, 2004
- Narendra S. Khandekar
- G11 - INFORMATION STORAGE
Information Patent Application
Two dimensional data eye centering for source synchronous data tran...
- Publication number 20040123207
- Publication date Jun 24, 2004
- Intel Corporation
- John F. Zumkehr
- G11 - INFORMATION STORAGE
Information Patent Application
Memory system with burst length shorter than prefetch length
- Publication number 20030182513
- Publication date Sep 25, 2003
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method to track command signal occurrence for dram da...
- Publication number 20030145161
- Publication date Jul 31, 2003
- Narendra S. Khandekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method to track flag transitions for DRAM data transfer
- Publication number 20030145156
- Publication date Jul 31, 2003
- Narendra S. Khandekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distributed memory module cache command formatting
- Publication number 20030135693
- Publication date Jul 17, 2003
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distributed memory module cache
- Publication number 20030131181
- Publication date Jul 10, 2003
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distributed memory module cache writeback
- Publication number 20030126373
- Publication date Jul 3, 2003
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Segmented distributed memory module cache
- Publication number 20030126363
- Publication date Jul 3, 2003
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING

Howard S. David

Person

Patents Grantslast 30 patents

Stuffing bits on a memory bus between data bursts

Method and apparatus to limit memory power

Method and system to improve the operations of a registered memory...

Memory power management via dynamic memory operation states

Memory power estimation by means of calibrated weights and activity...

Method and system to improve the operations of a registered memory...

Adaptive memory frequency scaling

Power management using adaptive thermal throttling

Memory rank burst scheduling

Coarsely controlling memory power states

Multiple address outputs for programming the memory register set di...

Temperature sampling in electronic devices

System and method for memory phase shedding

Optimizing mode register set commands

Partial bank DRAM precharge

Distributed memory module cache writeback

System and method for thermal throttling of memory modules

Ballout for buffer

Side-by-side inverted memory address and command buses

Two dimensional data eye centering for source synchronous data tran...

Apparatus and method to track flag transitions for DRAM data transfer

Apparatus and method to track command signal occurrence for DRAM da...

Distributed memory module cache

Distributed memory module cache command formatting

Distributed memory module cache prefetch

Distributed memory module cache tag look-up

Segmented distributed memory module cache

Method of addressing individual memory devices on a memory module

Memory system with burst length shorter than prefetch length

Method and apparatus for sequencing system bus grants and disabling...

Patents Applicationslast 30 patents

HIERARCHICAL AND PARALLEL PARTITION NETWORKS

LINE CODING FOR LOW-RADIO NOISE MEMORY INTERFACES

METHOD AND SYSTEM TO IMPROVE THE OPERATIONS OF A REGISTERED MEMORY...

METHOD AND APPARATUS TO LIMIT MEMORY POWER

MEMORY POWER ESTIMATION BY MEANS OF CALIBRATED WEIGHTS AND ACTIVITY...

MEMORY POWER MANAGEMENT VIA DYNAMIC MEMORY OPERATION STATES

ADAPTIVE MEMORY FREQUENCY SCALING

METHOD AND SYSTEM TO IMPROVE THE OPERATIONS OF A REGISTERED MEMORY...

MEMORY RANK BURST SCHEDULING

SYSTEM AND METHOD FOR MEMORY PHASE SHEDDING

Optimizing mode register set commands

MULTIPLE ADDRESS OUTPUTS FOR PROGRAMMING THE MEMORY REGISTER SET DI...

Coarsely controlling memory power states

Power management using adaptive thermal throttling

Temperature sampling in electronic devices

Temperature sampling in electronic devices

Ballout for buffer

Side-by-side inverted memory address and command buses

System and method for thermal throttling of memory modules

Partial bank DRAM precharge

Partial bank DRAM refresh

Method of addressing individual memory devices on a memory module

Two dimensional data eye centering for source synchronous data tran...

Memory system with burst length shorter than prefetch length

Apparatus and method to track command signal occurrence for dram da...

Apparatus and method to track flag transitions for DRAM data transfer

Distributed memory module cache command formatting

Distributed memory module cache

Distributed memory module cache writeback

Segmented distributed memory module cache