Hsien-Feng Liu

Person

Chiayi City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor package with dual sides of metal routing
- Patent number 12,113,025
- Issue date Oct 8, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and method of manufacturing a semiconductor...
- Patent number 12,009,316
- Issue date Jun 11, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hsien-Wen Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package structure
- Patent number 11,798,898
- Issue date Oct 24, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hsiao-Wen Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip packages
- Patent number 11,756,928
- Issue date Sep 12, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shuo-Mao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structure and method for reducing polymer layer...
- Patent number 11,688,728
- Issue date Jun 27, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jing-Cheng Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Proximity detection sensor arrangements, devices, and methods
- Patent number 11,632,455
- Issue date Apr 18, 2023
- Analog Devices International Unlimited Company
- Xiangzhi Wu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit test method and structure thereof
- Patent number 11,532,524
- Issue date Dec 20, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hsien-Wen Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with dual sides of metal routing
- Patent number 11,456,257
- Issue date Sep 27, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and formation method of package structure with fan-out st...
- Patent number 11,430,739
- Issue date Aug 30, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip wafer level packages
- Patent number 11,342,306
- Issue date May 24, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shuo-Mao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and formation method for chip package
- Patent number 11,329,031
- Issue date May 10, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jui-Pin Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming multi-chip wafer level packages
- Patent number 11,189,596
- Issue date Nov 30, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shuo-Mao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level mold chase
- Patent number 11,114,313
- Issue date Sep 7, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hsien-Wen Liu
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Information Patent Grant
Integrated circuit structure and method for reducing polymer layer...
- Patent number 11,081,475
- Issue date Aug 3, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jing-Cheng Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated fan-out package, package-on-package structure, and manuf...
- Patent number 11,075,132
- Issue date Jul 27, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package structure with buffer layer sandwiched between encapsulatio...
- Patent number 11,056,445
- Issue date Jul 6, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hsiao-Wen Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated fan-out packages
- Patent number 10,879,162
- Issue date Dec 29, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with redistribution structure and pre-made su...
- Patent number 10,867,924
- Issue date Dec 15, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level package (WLP) and method for forming the same
- Patent number 10,861,801
- Issue date Dec 8, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip wafer level packages and methods of forming the same
- Patent number 10,763,239
- Issue date Sep 1, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Shuo-Mao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and formation method for chip package
- Patent number 10,748,882
- Issue date Aug 18, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jui-Pin Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package structure and method for forming the same
- Patent number 10,529,671
- Issue date Jan 7, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hsiao-Wen Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level package (WLP) and method for forming the same
- Patent number 10,510,690
- Issue date Dec 17, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid memory system and method of operating the same
- Patent number 10,437,499
- Issue date Oct 8, 2019
- NANYA TECHNOLOGY CORPORATION
- Chung-Hsun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM and method of operating the same in an hierarchical memory system
- Patent number 10,380,024
- Issue date Aug 13, 2019
- NANYA TECHNOLOGY CORPORATION
- Chung-Hsun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM and method for determining binary logic using a test voltage l...
- Patent number 10,354,713
- Issue date Jul 16, 2019
- NANYA TECHNOLOGY CORPORATION
- Chung-Hsun Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Using metal-containing layer to reduce carrier shock in package for...
- Patent number 10,354,988
- Issue date Jul 16, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated fan-out packages
- Patent number 10,347,574
- Issue date Jul 9, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for preserving data in volatile memory
- Patent number 10,338,831
- Issue date Jul 2, 2019
- NANYA TECHNOLOGY CORPORATION
- Chung-Hsun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM and method for operating the same
- Patent number 10,332,579
- Issue date Jun 25, 2019
- NANYA TECHNOLOGY CORPORATION
- Chung-Hsun Lee
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR STRUCTURE AND TEST METHOD THEREOF
- Publication number 20240387297
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsien-Wen Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MANUFACTURING METHOD OF PACKAGE-ON-PACKAGE STRUCTURE AND MANUFACTUR...
- Publication number 20240387308
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND SYSTEMS FOR IMPROVING SURFACE MOUNT JOINDER
- Publication number 20240389239
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hsien-Wen Liu
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHODS AND SYSTEMS FOR IMPROVING SURFACE MOUNT JOINDER
- Publication number 20230422403
- Publication date Dec 28, 2023
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- Hsien-Wen Liu
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
MULTI-CHIP PACKAGES AND METHODS OF FORMING THE SAME
- Publication number 20230369287
- Publication date Nov 16, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shuo-Mao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NETWORK COMMUNICATION DEVICE WITH ANTENNA FRAME
- Publication number 20230327340
- Publication date Oct 12, 2023
- SERCOMM CORPORATION
- Hsien-Wen Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Package with Dual Sides of Metal Routing
- Publication number 20220375843
- Publication date Nov 24, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT TEST METHOD AND STRUCTURE THEREOF
- Publication number 20220367296
- Publication date Nov 17, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsien-Wen Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE WITH FAN-OUT STRUCTURE
- Publication number 20220352085
- Publication date Nov 3, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Hao TSAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR...
- Publication number 20220352089
- Publication date Nov 3, 2022
- Taiwan Semiconductor Manufacturing company Ltd.
- HSIEN-WEN LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGES
- Publication number 20220246579
- Publication date Aug 4, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shuo-Mao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT TEST METHOD AND STRUCTURE THEREOF
- Publication number 20220028748
- Publication date Jan 27, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsien-Wen Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED FAN-OUT PACKAGE, PACKAGE-ON-PACKAGE STRUCTURE, AND MANUF...
- Publication number 20210358824
- Publication date Nov 18, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Structure and Method for Reducing Polymer Layer...
- Publication number 20210351173
- Publication date Nov 11, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jing-Cheng Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE
- Publication number 20210335728
- Publication date Oct 28, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hsiao-Wen LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROXIMITY DETECTION SENSOR ARRANGEMENTS, DEVICES, AND METHODS
- Publication number 20210281676
- Publication date Sep 9, 2021
- Analog Devices International Unlimited Company
- Xiangzhi WU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTI-CHIP WAFER LEVEL PACKAGES
- Publication number 20200395335
- Publication date Dec 17, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shuo-Mao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and Formation Method for Chip Package
- Publication number 20200381407
- Publication date Dec 3, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Pin Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL MOLD CHASE
- Publication number 20200365421
- Publication date Nov 19, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsien-Wen LIU
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Information Patent Application
METHODS OF FORMING MULTI-CHIP WAFER LEVEL PACKAGES
- Publication number 20200343220
- Publication date Oct 29, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shuo-Mao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE
- Publication number 20200135661
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsiao-Wen LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND FORMATION METHOD OF PACKAGE STRUCTURE WITH FAN-OUT ST...
- Publication number 20200135653
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Po-Hao TSAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Level Package (WLP) and Method for Forming the Same
- Publication number 20200098705
- Publication date Mar 26, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME
- Publication number 20200013707
- Publication date Jan 9, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH DUAL SIDES OF METAL ROUTING
- Publication number 20200006234
- Publication date Jan 2, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF OPERATING THE SAME
- Publication number 20190196902
- Publication date Jun 27, 2019
- NANYA TECHNOLOGY CORPORATION
- Chung-Hsun LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF OPERATING THE SAME
- Publication number 20190196726
- Publication date Jun 27, 2019
- NANYA TECHNOLOGY CORPORATION
- Chung-Hsun LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
- Publication number 20190196733
- Publication date Jun 27, 2019
- NANYA TECHNOLOGY CORPORATION
- Chung-Hsun LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM AND METHOD OF OPERATING THE SAME
- Publication number 20190171572
- Publication date Jun 6, 2019
- NANYA TECHNOLOGY CORPORATION
- Chung-Hsun LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM AND METHOD FOR OPERATING THE SAME
- Publication number 20190164589
- Publication date May 30, 2019
- NANYA TECHNOLOGY CORPORATION
- Chung-Hsun LEE
- G11 - INFORMATION STORAGE

Hsien-Feng Liu

Person

Patents Grantslast 30 patents

Semiconductor package with dual sides of metal routing

Semiconductor structure and method of manufacturing a semiconductor...

Package structure

Multi-chip packages

Integrated circuit structure and method for reducing polymer layer...

Proximity detection sensor arrangements, devices, and methods

Integrated circuit test method and structure thereof

Semiconductor package with dual sides of metal routing

Structure and formation method of package structure with fan-out st...

Multi-chip wafer level packages

Structure and formation method for chip package

Methods of forming multi-chip wafer level packages

Wafer level mold chase

Integrated circuit structure and method for reducing polymer layer...

Integrated fan-out package, package-on-package structure, and manuf...

Package structure with buffer layer sandwiched between encapsulatio...

Integrated fan-out packages

Semiconductor package with redistribution structure and pre-made su...

Wafer level package (WLP) and method for forming the same

Multi-chip wafer level packages and methods of forming the same

Structure and formation method for chip package

Package structure and method for forming the same

Wafer level package (WLP) and method for forming the same

Hybrid memory system and method of operating the same

DRAM and method of operating the same in an hierarchical memory system

DRAM and method for determining binary logic using a test voltage l...

Using metal-containing layer to reduce carrier shock in package for...

Integrated fan-out packages

System and method for preserving data in volatile memory

DRAM and method for operating the same

Patents Applicationslast 30 patents

SEMICONDUCTOR STRUCTURE AND TEST METHOD THEREOF

MANUFACTURING METHOD OF PACKAGE-ON-PACKAGE STRUCTURE AND MANUFACTUR...

METHODS AND SYSTEMS FOR IMPROVING SURFACE MOUNT JOINDER

METHODS AND SYSTEMS FOR IMPROVING SURFACE MOUNT JOINDER

MULTI-CHIP PACKAGES AND METHODS OF FORMING THE SAME

NETWORK COMMUNICATION DEVICE WITH ANTENNA FRAME

Semiconductor Package with Dual Sides of Metal Routing

INTEGRATED CIRCUIT TEST METHOD AND STRUCTURE THEREOF

PACKAGE STRUCTURE WITH FAN-OUT STRUCTURE

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR...

MULTI-CHIP PACKAGES

INTEGRATED CIRCUIT TEST METHOD AND STRUCTURE THEREOF

INTEGRATED FAN-OUT PACKAGE, PACKAGE-ON-PACKAGE STRUCTURE, AND MANUF...

Integrated Circuit Structure and Method for Reducing Polymer Layer...

PACKAGE STRUCTURE

PROXIMITY DETECTION SENSOR ARRANGEMENTS, DEVICES, AND METHODS

MULTI-CHIP WAFER LEVEL PACKAGES

Structure and Formation Method for Chip Package

WAFER LEVEL MOLD CHASE

METHODS OF FORMING MULTI-CHIP WAFER LEVEL PACKAGES

PACKAGE STRUCTURE

STRUCTURE AND FORMATION METHOD OF PACKAGE STRUCTURE WITH FAN-OUT ST...

Wafer Level Package (WLP) and Method for Forming the Same

INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME

SEMICONDUCTOR PACKAGE WITH DUAL SIDES OF METAL ROUTING

DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF OPERATING THE SAME

DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF OPERATING THE SAME

HYBRID MEMORY SYSTEM AND METHOD OF OPERATING THE SAME

DRAM AND METHOD OF OPERATING THE SAME

DRAM AND METHOD FOR OPERATING THE SAME