Hsien-Yu Pan

Person

Hsinchu City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system to balance ground bounce
- Patent number 12,100,436
- Issue date Sep 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array circuit and method of manufacturing same
- Patent number 12,074,156
- Issue date Aug 27, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array circuit and method of manufacturing same
- Patent number 12,029,023
- Issue date Jul 2, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static random access memory with write assist circuit
- Patent number 11,948,627
- Issue date Apr 2, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor chip having memory and logic cells
- Patent number 11,769,533
- Issue date Sep 26, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system to balance ground bounce
- Patent number 11,657,870
- Issue date May 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array circuit and method of manufacturing same
- Patent number 11,637,108
- Issue date Apr 25, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static random access memory with write assist circuit
- Patent number 11,423,977
- Issue date Aug 23, 2022
- Taiwan Semiconductor Manufacturing Co. LTD
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi word line assertion
- Patent number 11,322,198
- Issue date May 3, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell
- Patent number 11,176,997
- Issue date Nov 16, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system to balance ground bounce
- Patent number 11,074,966
- Issue date Jul 27, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip having memory and logic cells
- Patent number 11,062,739
- Issue date Jul 13, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell and method of manufacturing the same
- Patent number 11,018,142
- Issue date May 25, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SRAM cell for interleaved wordline scheme
- Patent number 10,971,217
- Issue date Apr 6, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array circuit and method of manufacturing the same
- Patent number 10,964,683
- Issue date Mar 30, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell
- Patent number 10,964,389
- Issue date Mar 30, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device
- Patent number 10,943,667
- Issue date Mar 9, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi word line assertion
- Patent number 10,892,008
- Issue date Jan 12, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Variation tolerant read assist circuit for SRAM
- Patent number 10,832,765
- Issue date Nov 10, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM cell for interleaved wordline scheme
- Patent number 10,770,131
- Issue date Sep 8, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory with write assist circuit
- Patent number 10,734,066
- Issue date Aug 4, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell
- Patent number 10,714,181
- Issue date Jul 14, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of providing layout design of SRAM cell
- Patent number 10,510,739
- Issue date Dec 17, 2019
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hidehiro Fujiwara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SRAM cell for interleaved wordline scheme
- Patent number 10,276,231
- Issue date Apr 30, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout design for manufacturing a memory cell
- Patent number 10,276,579
- Issue date Apr 30, 2019
- Taiwan Semiconductor Manufacturing Company Limited
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM cell for interleaved wordline scheme
- Patent number 9,886,996
- Issue date Feb 6, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout scheme and method for forming device cells in semiconductor...
- Patent number 9,853,035
- Issue date Dec 26, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsien-Yu Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout scheme and method for forming device cells in semiconductor...
- Patent number 8,928,113
- Issue date Jan 6, 2015
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsien-Yu Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memories
- Patent number 8,576,655
- Issue date Nov 5, 2013
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Wei Min Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with low sensing margin and high device variation t...
- Patent number 8,570,823
- Issue date Oct 29, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yen-Huei Chen
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE
- Publication number 20250054537
- Publication date Feb 13, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME
- Publication number 20240363616
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro FUJIWARA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME
- Publication number 20240357788
- Publication date Oct 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro FUJIWARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT
- Publication number 20240203488
- Publication date Jun 20, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro FUJIWARA
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE
- Publication number 20230377640
- Publication date Nov 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME
- Publication number 20230301049
- Publication date Sep 21, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro FUJIWARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT
- Publication number 20220383947
- Publication date Dec 1, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro FUJIWARA
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE
- Publication number 20210350849
- Publication date Nov 11, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR CHIP HAVING MEMORY AND LOGIC CELLS
- Publication number 20210343317
- Publication date Nov 4, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME
- Publication number 20210272967
- Publication date Sep 2, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro FUJIWARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME
- Publication number 20210217742
- Publication date Jul 15, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro FUJIWARA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL
- Publication number 20210201999
- Publication date Jul 1, 2021
- Taiwan Semiconductor Manufacturing Co., LTD
- Hidehiro FUJIWARA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI WORD LINE ASSERTION
- Publication number 20210098054
- Publication date Apr 1, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR CHIP
- Publication number 20200411063
- Publication date Dec 31, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
Static Random Access Memory with Write Assist Circuit
- Publication number 20200411084
- Publication date Dec 31, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro FUJIWARA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SRAM CELL FOR INTERLEAVED WORDLINE SCHEME
- Publication number 20200372951
- Publication date Nov 26, 2020
- Taiwan Semiconductor Manufacturing Co., LTD
- Hidehiro Fujiwara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL
- Publication number 20200321054
- Publication date Oct 8, 2020
- Taiwan Semiconductor Manufactring Co., Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE
- Publication number 20200135288
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE
- Publication number 20200135268
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL AND METHOD OF MANUFACTURING THE SAME
- Publication number 20200020699
- Publication date Jan 16, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro FUJIWARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Variation Tolerant Read Assist Circuit for SRAM
- Publication number 20200005858
- Publication date Jan 2, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro FUJIWARA
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI WORD LINE ASSERTION
- Publication number 20190385671
- Publication date Dec 19, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM CELL FOR INTERLEAVED WORDLINE SCHEME
- Publication number 20190237134
- Publication date Aug 1, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Hidehiro Fujiwara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING THE SAME
- Publication number 20190067264
- Publication date Feb 28, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro FUJIWARA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT
- Publication number 20190035455
- Publication date Jan 31, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro FUJIWARA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD OF PROVIDING LAYOUT DESIGN OF SRAM CELL
- Publication number 20180166433
- Publication date Jun 14, 2018
- Taiwan Semiconductor Manufacturing company Ltd.
- HIDEHIRO FUJIWARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM CELL FOR INTERLEAVED WORDLINE SCHEME
- Publication number 20180158510
- Publication date Jun 7, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Hidehiro Fujiwara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL
- Publication number 20180151226
- Publication date May 31, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Hidehiro FUJIWARA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layout Design for Manufacturing a Memory Cell
- Publication number 20170271342
- Publication date Sep 21, 2017
- Taiwan Semiconductor Manufacturing Company Limited
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM CELL FOR INTERLEAVED WORDLINE SCHEME
- Publication number 20170110181
- Publication date Apr 20, 2017
- Taiwan Semiconductor Manufacturing Co., LTD
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE

Hsien-Yu Pan

Person

Patents Grantslast 30 patents

Method and system to balance ground bounce

Memory array circuit and method of manufacturing same

Memory array circuit and method of manufacturing same

Static random access memory with write assist circuit

Semiconductor chip having memory and logic cells

Method and system to balance ground bounce

Memory array circuit and method of manufacturing same

Static random access memory with write assist circuit

Multi word line assertion

Memory cell

Method and system to balance ground bounce

Semiconductor chip having memory and logic cells

Memory cell and method of manufacturing the same

SRAM cell for interleaved wordline scheme

Memory array circuit and method of manufacturing the same

Memory cell

Memory device

Multi word line assertion

Variation tolerant read assist circuit for SRAM

SRAM cell for interleaved wordline scheme

Static random access memory with write assist circuit

Memory cell

Method of providing layout design of SRAM cell

SRAM cell for interleaved wordline scheme

Layout design for manufacturing a memory cell

SRAM cell for interleaved wordline scheme

Layout scheme and method for forming device cells in semiconductor...

Layout scheme and method for forming device cells in semiconductor...

Semiconductor memories

Sense amplifier with low sensing margin and high device variation t...

Patents Applicationslast 30 patents

METHOD AND SYSTEM TO BALANCE GROUND BOUNCE

MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME

MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME

STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT

METHOD AND SYSTEM TO BALANCE GROUND BOUNCE

MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME

STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT

METHOD AND SYSTEM TO BALANCE GROUND BOUNCE

SEMICONDUCTOR CHIP HAVING MEMORY AND LOGIC CELLS

MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME

MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME

MEMORY CELL

MULTI WORD LINE ASSERTION

SEMICONDUCTOR CHIP

Static Random Access Memory with Write Assist Circuit

SRAM CELL FOR INTERLEAVED WORDLINE SCHEME

MEMORY CELL

MEMORY DEVICE

METHOD AND SYSTEM TO BALANCE GROUND BOUNCE

MEMORY CELL AND METHOD OF MANUFACTURING THE SAME

Variation Tolerant Read Assist Circuit for SRAM

MULTI WORD LINE ASSERTION

SRAM CELL FOR INTERLEAVED WORDLINE SCHEME

MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING THE SAME

STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT

METHOD OF PROVIDING LAYOUT DESIGN OF SRAM CELL

SRAM CELL FOR INTERLEAVED WORDLINE SCHEME

MEMORY CELL

Layout Design for Manufacturing a Memory Cell

SRAM CELL FOR INTERLEAVED WORDLINE SCHEME