Hsin-Yu Chen

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Burst read with flexible burst length for on-chip memory
- Patent number 12,087,353
- Issue date Sep 10, 2024
- ARM Limited
- Edward Martin McCombs
- G11 - INFORMATION STORAGE
Information Patent Grant
Power-up header circuitry for multi-bank memory
- Patent number 12,068,025
- Issue date Aug 20, 2024
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Grant
System cache peak power management
- Patent number 11,935,580
- Issue date Mar 19, 2024
- ARM Limited
- Edward Martin McCombs
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses of configurable integrated circuits
- Patent number 11,017,142
- Issue date May 25, 2021
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level shift latch circuitry
- Patent number 11,005,461
- Issue date May 11, 2021
- ARM Limited
- Andy Wangkun Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Level shifter with bypass
- Patent number 10,535,386
- Issue date Jan 14, 2020
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit with impedance elements connected to sources and drains of...
- Patent number 10,177,760
- Issue date Jan 8, 2019
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double pumped memory techniques
- Patent number 9,627,022
- Issue date Apr 18, 2017
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of controlling leakage current within such...
- Patent number 9,147,451
- Issue date Sep 29, 2015
- ARM Limited
- Yew Keong Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Improving read stability of a semiconductor memory
- Patent number 8,830,783
- Issue date Sep 9, 2014
- ARM Limited
- Sachin Satish Idgunji
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling a voltage level of an access signal to reduce access di...
- Patent number 8,611,172
- Issue date Dec 17, 2013
- ARM Limited
- Amaranth Shyanmugam
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuitry with write boost and write assist
- Patent number 8,493,810
- Issue date Jul 23, 2013
- ARM Limited
- Nicolaas Klarinus Johannes van Winkelhoff
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline voltage control within a memory
- Patent number 8,315,123
- Issue date Nov 20, 2012
- ARM Limited
- Yew Keong Chong
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Burst Read with Flexible Burst Length for On-Chip Memory
- Publication number 20240055047
- Publication date Feb 15, 2024
- ARM Limited
- Edward Martin McCombs
- G11 - INFORMATION STORAGE
Information Patent Application
Power-Up Header Circuitry for Multi-Bank Memory
- Publication number 20240005983
- Publication date Jan 4, 2024
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Bitline Precharge Techniques
- Publication number 20230402092
- Publication date Dec 14, 2023
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
System Cache Peak Power Management
- Publication number 20230154526
- Publication date May 18, 2023
- ARM Limited
- Edward Martin McCombs
- G11 - INFORMATION STORAGE
Information Patent Application
Level Shift Latch Circuitry
- Publication number 20190379364
- Publication date Dec 12, 2019
- ARM Limited
- Andy Wangkun Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit with Impedance Elements Connected to Sources and Drains of...
- Publication number 20190007043
- Publication date Jan 3, 2019
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Level Shifter with Bypass
- Publication number 20180342271
- Publication date Nov 29, 2018
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Double Pumped Memory Techniques
- Publication number 20160064054
- Publication date Mar 3, 2016
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD OF CONTROLLING LEAKAGE CURRENT WITHIN SUCH...
- Publication number 20140286096
- Publication date Sep 25, 2014
- ARM Limited
- Yew Keong CHONG
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLING A VOLTAGE LEVEL OF AN ACCESS SIGNAL TO REDUCE ACCESS DI...
- Publication number 20130308407
- Publication date Nov 21, 2013
- ARM Limited
- Amaranth Shyanmugam
- G11 - INFORMATION STORAGE
Information Patent Application
Memory circuitry with write boost and write assist
- Publication number 20120287733
- Publication date Nov 15, 2012
- ARM Limited
- Nicolaas Klarinus Johannes van Winkelhoff
- G11 - INFORMATION STORAGE
Information Patent Application
Read stability of a semiconductor memory
- Publication number 20120170390
- Publication date Jul 5, 2012
- ARM Limited
- Sachin Satish Idgunji
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline voltage control within a memory
- Publication number 20120155194
- Publication date Jun 21, 2012
- ARM Limited
- Yew Keong Chong
- G11 - INFORMATION STORAGE

Hsin-Yu Chen

Person

Patents Grantslast 30 patents

Burst read with flexible burst length for on-chip memory

Power-up header circuitry for multi-bank memory

System cache peak power management

Methods and apparatuses of configurable integrated circuits

Level shift latch circuitry

Level shifter with bypass

Circuit with impedance elements connected to sources and drains of...

Double pumped memory techniques

Memory device and method of controlling leakage current within such...

Improving read stability of a semiconductor memory

Controlling a voltage level of an access signal to reduce access di...

Memory circuitry with write boost and write assist

Wordline voltage control within a memory

Patents Applicationslast 30 patents

Burst Read with Flexible Burst Length for On-Chip Memory

Power-Up Header Circuitry for Multi-Bank Memory

Bitline Precharge Techniques

System Cache Peak Power Management

Level Shift Latch Circuitry

Circuit with Impedance Elements Connected to Sources and Drains of...

Level Shifter with Bypass

Double Pumped Memory Techniques

MEMORY DEVICE AND METHOD OF CONTROLLING LEAKAGE CURRENT WITHIN SUCH...

CONTROLLING A VOLTAGE LEVEL OF AN ACCESS SIGNAL TO REDUCE ACCESS DI...

Memory circuitry with write boost and write assist

Read stability of a semiconductor memory

Wordline voltage control within a memory