Hua Xiang

Person

Ossining, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power staple avoidance for routing via reduction
- Patent number 12,277,375
- Issue date Apr 15, 2025
- International Business Machines Corporation
- Hua Xiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-stage electronic design automation parameter tuning
- Patent number 12,124,789
- Issue date Oct 22, 2024
- International Business Machines Corporation
- Gi-Joon Nam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
White space insertion for enhanced routability
- Patent number 11,120,192
- Issue date Sep 14, 2021
- International Business Machines Corporation
- Hua Xiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic SADP region generation
- Patent number 11,087,062
- Issue date Aug 10, 2021
- International Business Machines Corporation
- Hua Xiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Autonomous placement to satisfy self-aligned double patterning cons...
- Patent number 10,796,064
- Issue date Oct 6, 2020
- International Business Machines Corporation
- Hua Xiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of predicting problematic areas for lithography i...
- Patent number 9,075,944
- Issue date Jul 7, 2015
- Mentor Graphics Corporation
- Timothy A. Brunner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Relative ordering circuit synthesis
- Patent number 8,756,541
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network flow based datapath bit slicing
- Patent number 8,566,761
- Issue date Oct 22, 2013
- International Business Machines Corporation
- Hua Xiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Soft hierarchy-based physical synthesis for large-scale, high-perfo...
- Patent number 8,516,412
- Issue date Aug 20, 2013
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structured latch and local-clock-buffer planning
- Patent number 8,495,552
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of predicting problematic areas for lithography i...
- Patent number 8,484,586
- Issue date Jul 9, 2013
- Mentor Graphics Corporation
- Timothy A. Brunner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Converged large block and structured synthesis for high performance...
- Patent number 8,271,920
- Issue date Sep 18, 2012
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network flow based module bottom surface metal pin assignment
- Patent number 8,261,226
- Issue date Sep 4, 2012
- International Business Machines Corporation
- Wiren Dale Becker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of predicting problematic areas for lithography i...
- Patent number 8,239,789
- Issue date Aug 7, 2012
- International Business Machines Corporation
- Timothy A. Brunner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, method and computer program product for fast simulation...
- Patent number 8,117,568
- Issue date Feb 14, 2012
- International Business Machines Corporation
- Hua Xiang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System and method of predicting problematic areas for lithography i...
- Patent number 8,001,495
- Issue date Aug 16, 2011
- International Business Machines Corporation
- Timothy A. Brunner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stage mitigation of interconnect variability
- Patent number 7,930,669
- Issue date Apr 19, 2011
- International Business Machines Corporation
- Mark A. Lavin
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System and method for global circuit routing incorporating estimati...
- Patent number 7,685,553
- Issue date Mar 23, 2010
- International Business Machines Corporation
- Evanthia Papadopoulou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flow based package pin assignment
- Patent number 7,533,360
- Issue date May 12, 2009
- International Business Machines Corporation
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design stage mitigation of interconnect variability
- Patent number 7,448,014
- Issue date Nov 4, 2008
- International Business Machines Corporation
- Mark A. Lavin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BIT FLIP AWARE LATCH PLACEMENT
- Publication number 20240104282
- Publication date Mar 28, 2024
- International Business Machines Corporation
- Benjamin Neil Trombley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHORT NET PIN ALIGNMENT FOR ROUTING
- Publication number 20230306179
- Publication date Sep 28, 2023
- International Business Machines Corporation
- Hua XIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER STAPLE AVOIDANCE FOR ROUTING VIA REDUCTION
- Publication number 20230237233
- Publication date Jul 27, 2023
- International Business Machines Corporation
- Hua XIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-STAGE ELECTRONIC DESIGN AUTOMATION PARAMETER TUNING
- Publication number 20230195993
- Publication date Jun 22, 2023
- International Business Machines Corporation
- Gi-Joon Nam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS PLACEMENT TO SATISFY SELF-ALIGNED DOUBLE PATTERNING CONS...
- Publication number 20200057836
- Publication date Feb 20, 2020
- International Business Machines Corporation
- Hua Xiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Structured Latch and Local-Clock-Buffer Planning
- Publication number 20130326451
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY I...
- Publication number 20130286370
- Publication date Oct 31, 2013
- Mentor Graphics Corporation
- Timothy A. Brunner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RELATIVE ORDERING CIRCUIT SYNTHESIS
- Publication number 20130263068
- Publication date Oct 3, 2013
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK FLOW BASED DATAPATH BIT SLICING
- Publication number 20130132915
- Publication date May 23, 2013
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFT HIERARCHY-BASED PHYSICAL SYNTHESIS FOR LARGE-SCALE, HIGH-PERFO...
- Publication number 20130055176
- Publication date Feb 28, 2013
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY I...
- Publication number 20120254812
- Publication date Oct 4, 2012
- International Business Machines Corporation
- Timothy A. Brunner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERGED LARGE BLOCK AND STRUCTURED SYNTHESIS FOR HIGH PERFORMANCE...
- Publication number 20120054699
- Publication date Mar 1, 2012
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY I...
- Publication number 20110184715
- Publication date Jul 28, 2011
- International Business Machines Corporation
- Timothy A. BRUNNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, Method and Computer Program Product for Fast Stimulation...
- Publication number 20100077372
- Publication date Mar 25, 2010
- International Business Machines Corporation
- Hua Xiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY I...
- Publication number 20090265679
- Publication date Oct 22, 2009
- International Business Machines Corporation
- Timothy A. Brunner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STAGE MITIGATION OF INTERCONNECT VARIABILITY
- Publication number 20090019415
- Publication date Jan 15, 2009
- Mark A. Lavin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR GLOBAL CIRCUIT ROUTING INCORPORATING ESTIMATI...
- Publication number 20080256502
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Evanthia Papadopoulou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design stage mitigation of interconnect variability
- Publication number 20070214446
- Publication date Sep 13, 2007
- International Business Machines Corporation
- Mark A. Lavin
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Power staple avoidance for routing via reduction

Multi-stage electronic design automation parameter tuning

White space insertion for enhanced routability

Dynamic SADP region generation

Autonomous placement to satisfy self-aligned double patterning cons...

System and method of predicting problematic areas for lithography i...

Relative ordering circuit synthesis

Network flow based datapath bit slicing

Soft hierarchy-based physical synthesis for large-scale, high-perfo...

Structured latch and local-clock-buffer planning

System and method of predicting problematic areas for lithography i...

Converged large block and structured synthesis for high performance...

Network flow based module bottom surface metal pin assignment

System and method of predicting problematic areas for lithography i...

Apparatus, method and computer program product for fast simulation...

System and method of predicting problematic areas for lithography i...

Stage mitigation of interconnect variability

System and method for global circuit routing incorporating estimati...

Flow based package pin assignment

Design stage mitigation of interconnect variability

Patents Applicationslast 30 patents

BIT FLIP AWARE LATCH PLACEMENT

SHORT NET PIN ALIGNMENT FOR ROUTING

POWER STAPLE AVOIDANCE FOR ROUTING VIA REDUCTION

MULTI-STAGE ELECTRONIC DESIGN AUTOMATION PARAMETER TUNING

AUTONOMOUS PLACEMENT TO SATISFY SELF-ALIGNED DOUBLE PATTERNING CONS...

Structured Latch and Local-Clock-Buffer Planning

SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY I...

RELATIVE ORDERING CIRCUIT SYNTHESIS

NETWORK FLOW BASED DATAPATH BIT SLICING

SOFT HIERARCHY-BASED PHYSICAL SYNTHESIS FOR LARGE-SCALE, HIGH-PERFO...

SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY I...

CONVERGED LARGE BLOCK AND STRUCTURED SYNTHESIS FOR HIGH PERFORMANCE...

SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY I...

Apparatus, Method and Computer Program Product for Fast Stimulation...

SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY I...

STAGE MITIGATION OF INTERCONNECT VARIABILITY

SYSTEM AND METHOD FOR GLOBAL CIRCUIT ROUTING INCORPORATING ESTIMATI...

Design stage mitigation of interconnect variability