Huajun Wen

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic power meter with improved accuracy and single cycle resolution
- Patent number 10,345,882
- Issue date Jul 9, 2019
- Mediatek Inc.
- Huajun Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing power grid noise in a processor while minimizing performan...
- Patent number 9,146,772
- Issue date Sep 29, 2015
- International Business Machines Corporation
- Lee E. Eisen
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Reducing power grid noise in a processor while minimizing performan...
- Patent number 9,141,421
- Issue date Sep 22, 2015
- International Business Machines Corporation
- Lee E. Eisen
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Minimizing power consumption for fixed-frequency processing unit op...
- Patent number 9,052,905
- Issue date Jun 9, 2015
- International Business Machines Corporation
- Malcolm S. Allen-Ware
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Minimizing power consumption for fixed-frequency processing unit op...
- Patent number 8,943,341
- Issue date Jan 27, 2015
- International Business Machines Corporation
- Malcolm S. Allen-Ware
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Processor voltage regulation
- Patent number 8,812,879
- Issue date Aug 19, 2014
- International Business Machines Corporation
- Huajun Wen
- G05 - CONTROLLING REGULATING
Information Patent Grant
Redundancy-free circuits for zero counters
- Patent number 8,180,815
- Issue date May 15, 2012
- International Business Machines Corporation
- Aleksandr Kaplun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundancy-free circuits for zero counters
- Patent number 7,461,110
- Issue date Dec 2, 2008
- International Business Machines Corporation
- Aleksandr Kaplun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid carry look ahead/carry select adder including carry logic ge...
- Patent number 7,206,802
- Issue date Apr 17, 2007
- International Business Machines Corporation
- Huajun Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for designing a circuit wherein a single timing a...
- Patent number 7,024,647
- Issue date Apr 4, 2006
- International Business Machines Corporation
- Huajun Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase manipulation of intertwined bus signals for reduction of host...
- Patent number 6,718,420
- Issue date Apr 6, 2004
- International Business Machines Corporation
- John Thomas Badar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic phase splitter circuit and method for low-noise and simulta...
- Patent number 6,664,836
- Issue date Dec 16, 2003
- International Business Machines Corporation
- Huajun Wen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Edge triggered latch with symmetrical paths from clock to data outputs
- Patent number 6,492,856
- Issue date Dec 10, 2002
- International Business Machines Corporation
- Nobuo Kojima
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Edge-triggered latch with balanced pass-transistor logic trigger
- Patent number 6,445,217
- Issue date Sep 3, 2002
- International Business Machines Corporation
- Nobuo Kojima
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Edge triggered latch with symmetrical paths from clock to data outputs
- Patent number 6,437,625
- Issue date Aug 20, 2002
- International Business Machines Corporation
- Nobuo Kojima
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Edge-triggered latch with symmetric complementary pass-transistor l...
- Patent number 6,437,624
- Issue date Aug 20, 2002
- International Business Machines Corporation
- Nobuo Kojima
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for utilizing hostile-switching neighbors to impr...
- Patent number 6,407,574
- Issue date Jun 18, 2002
- International Business Machines Corporation
- Huajun Wen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differential force microscope
- Patent number 6,085,580
- Issue date Jul 11, 2000
- International Business Machines Corporation
- Rudolf Ludeke
- B82 - NANO-TECHNOLOGY

Patents Applicationslast 30 patents

Information Patent Application
Dynamic Power Meter with Improved Accuracy and Single Cycle Resolution
- Publication number 20160291068
- Publication date Oct 6, 2016
- MEDIATEK INC.
- Huajun Wen
- G01 - MEASURING TESTING
Information Patent Application
REDUCING POWER GRID NOISE IN A PROCESSOR WHILE MINIMIZING PERFORMAN...
- Publication number 20140157277
- Publication date Jun 5, 2014
- International Business Machines Corporation
- Lee E. Eisen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING POWER GRID NOISE IN A PROCESSOR WHILE MINIMIZING PERFORMAN...
- Publication number 20140157033
- Publication date Jun 5, 2014
- International Business Machines Corporation
- Lee E. Eisen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Minimizing Power Consumption for Fixed-Frequency Processing Unit Op...
- Publication number 20130268785
- Publication date Oct 10, 2013
- International Business Machines Corporation
- Malcolm S. Allen-Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Minimizing Power Consumption for Fixed-Frequency Processing Unit Op...
- Publication number 20130268786
- Publication date Oct 10, 2013
- International Business Machines Corporation
- Malcolm S. Allen-Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR VOLTAGE REGULATION
- Publication number 20110161682
- Publication date Jun 30, 2011
- International Business Machines Corporation
- Huajun Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANCY-FREE CIRCUITS FOR ZERO COUNTERS
- Publication number 20080301209
- Publication date Dec 4, 2008
- Aleksandr Kaplun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Redundancy-free circuits for zero counters
- Publication number 20060265439
- Publication date Nov 23, 2006
- Aleksandr Kaplun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for designing a circuit wherein a single timing a...
- Publication number 20050015737
- Publication date Jan 20, 2005
- International Business Machines Corporation
- Huajun Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid carry look ahead/carry select adder including carry logic ge...
- Publication number 20040073593
- Publication date Apr 15, 2004
- International Business Machines Corporation
- Huajun Wen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EDGE TRIGGERED LATCH WITH SYMMETRICAL PATHS FROM CLOCK TO DATA OUTPUTS
- Publication number 20020196064
- Publication date Dec 26, 2002
- IBM Corporation
- Nobuo Kojima
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EDGE-TRIGGERED LATCH WITH BALANCED PASS-TRANSISTOR LOGIC TRIGGER
- Publication number 20020130693
- Publication date Sep 19, 2002
- International Business Machines Corporation
- Nobuo Kojima
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Dynamic power meter with improved accuracy and single cycle resolution

Reducing power grid noise in a processor while minimizing performan...

Reducing power grid noise in a processor while minimizing performan...

Minimizing power consumption for fixed-frequency processing unit op...

Minimizing power consumption for fixed-frequency processing unit op...

Processor voltage regulation

Redundancy-free circuits for zero counters

Redundancy-free circuits for zero counters

Hybrid carry look ahead/carry select adder including carry logic ge...

System and method for designing a circuit wherein a single timing a...

Phase manipulation of intertwined bus signals for reduction of host...

Dynamic phase splitter circuit and method for low-noise and simulta...

Edge triggered latch with symmetrical paths from clock to data outputs

Edge-triggered latch with balanced pass-transistor logic trigger

Edge triggered latch with symmetrical paths from clock to data outputs

Edge-triggered latch with symmetric complementary pass-transistor l...

Method and system for utilizing hostile-switching neighbors to impr...

Differential force microscope

Patents Applicationslast 30 patents

Dynamic Power Meter with Improved Accuracy and Single Cycle Resolution

REDUCING POWER GRID NOISE IN A PROCESSOR WHILE MINIMIZING PERFORMAN...

REDUCING POWER GRID NOISE IN A PROCESSOR WHILE MINIMIZING PERFORMAN...

Minimizing Power Consumption for Fixed-Frequency Processing Unit Op...

Minimizing Power Consumption for Fixed-Frequency Processing Unit Op...

PROCESSOR VOLTAGE REGULATION

REDUNDANCY-FREE CIRCUITS FOR ZERO COUNTERS

Redundancy-free circuits for zero counters

System and method for designing a circuit wherein a single timing a...

Hybrid carry look ahead/carry select adder including carry logic ge...

EDGE TRIGGERED LATCH WITH SYMMETRICAL PATHS FROM CLOCK TO DATA OUTPUTS

EDGE-TRIGGERED LATCH WITH BALANCED PASS-TRANSISTOR LOGIC TRIGGER