Huaming Hu

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Fremont, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Chip level scan chain planning for hierarchical design flows
- Patent number 7,657,850
- Issue date Feb 2, 2010
- Synopsys, Inc.
- Lin Huang
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Chip level scan chain planning for hierarchical design flows
- Publication number 20080141086
- Publication date Jun 12, 2008
- Synopsys, Inc.
- Lin Huang
- G01 - MEASURING TESTING