Human Boluki

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Munich, DE

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Patents Grantslast 30 patents

Information Patent Grant
Burn-in testing of circuits
- Patent number 10,180,455
- Issue date Jan 15, 2019
- Infineon Technologies AG
- Rex Kho
- G01 - MEASURING TESTING
Information Patent Grant
Optimized buffering for JTAG boundary scan nets
- Patent number 7,000,163
- Issue date Feb 14, 2006
- LSI Logic Corporation
- Juergen Dirks
- G01 - MEASURING TESTING
Information Patent Grant
Split and merge design flow concept for fast turnaround time of cir...
- Patent number 6,898,770
- Issue date May 24, 2005
- LSI Logic Corporation
- Human Boluki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test structures for simultaneous switching output (SSO) analysis
- Patent number 6,788,098
- Issue date Sep 7, 2004
- LSI Logic Corporation
- Alaa A. Alani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Timing driven interconnect analysis
- Patent number 6,532,577
- Issue date Mar 11, 2003
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BURN-IN TESTING OF CIRCUITS
- Publication number 20180335471
- Publication date Nov 22, 2018
- INFINEON TECHNOLOGIES AG
- Rex Kho
- G01 - MEASURING TESTING
Information Patent Application
Split and merge design flow concept for fast turnaround time
- Publication number 20040139408
- Publication date Jul 15, 2004
- Human Boluki
- G06 - COMPUTING CALCULATING COUNTING