Hung Ong

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Zero latency prefetching in caches
- Patent number 12,197,334
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch kill and revival in an instruction cache
- Patent number 11,977,491
- Issue date May 7, 2024
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch kill and revival in an instruction cache
- Patent number 11,620,236
- Issue date Apr 4, 2023
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch management in a hierarchical cache system
- Patent number 11,567,874
- Issue date Jan 31, 2023
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero latency prefetching in caches
- Patent number 11,474,944
- Issue date Oct 18, 2022
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch kill and revival in an instruction cache
- Patent number 11,314,660
- Issue date Apr 26, 2022
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch management in a hierarchical cache system
- Patent number 11,169,924
- Issue date Nov 9, 2021
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero latency prefetching in caches
- Patent number 10,929,296
- Issue date Feb 23, 2021
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch management in a hierarchical cache system
- Patent number 10,642,742
- Issue date May 5, 2020
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch kill and revival in an instruction cache
- Patent number 10,489,305
- Issue date Nov 26, 2019
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using L1 cache as re-order buffer
- Patent number 9,652,392
- Issue date May 16, 2017
- Texas Instruments Incorporated
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using L1 cache as re-order buffer
- Patent number 9,471,320
- Issue date Oct 18, 2016
- Texas Instruments Incorporated
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing current leakage in L1 program memory
- Patent number 8,977,878
- Issue date Mar 10, 2015
- Texas Instruments Incorporated
- Ramakrishnan Venkatasubramanian
- G11 - INFORMATION STORAGE
Information Patent Grant
Independent source read and destination write enhanced DMA
- Patent number 7,577,774
- Issue date Aug 18, 2009
- Texas Instruments Incorporated
- Sanjive Agarwala
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20250103503
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
- Publication number 20240256464
- Publication date Aug 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
- Publication number 20230251975
- Publication date Aug 10, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM
- Publication number 20230176975
- Publication date Jun 8, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20230004498
- Publication date Jan 5, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
- Publication number 20220245069
- Publication date Aug 4, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM
- Publication number 20220058127
- Publication date Feb 24, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20210141732
- Publication date May 13, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM
- Publication number 20200320006
- Publication date Oct 8, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
- Publication number 20200089622
- Publication date Mar 19, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM
- Publication number 20200057720
- Publication date Feb 20, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20190114263
- Publication date Apr 18, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING L1 CACHE AS RE-ORDER BUFFER
- Publication number 20170010967
- Publication date Jan 12, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING L1 CACHE AS RE-ORDER BUFFER
- Publication number 20160019151
- Publication date Jan 21, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing Current Leakage in L1 Program Memory
- Publication number 20120297225
- Publication date Nov 22, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Ramakrishnan Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Independent source read and destination write enhanced DMA
- Publication number 20060256796
- Publication date Nov 16, 2006
- Sanjive Agarwala
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Zero latency prefetching in caches

Prefetch kill and revival in an instruction cache

Prefetch kill and revival in an instruction cache

Prefetch management in a hierarchical cache system

Zero latency prefetching in caches

Prefetch kill and revival in an instruction cache

Prefetch management in a hierarchical cache system

Zero latency prefetching in caches

Prefetch management in a hierarchical cache system

Prefetch kill and revival in an instruction cache

Using L1 cache as re-order buffer

Using L1 cache as re-order buffer

Reducing current leakage in L1 program memory

Independent source read and destination write enhanced DMA

Patents Applicationslast 30 patents

ZERO LATENCY PREFETCHING IN CACHES

PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE

PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE

PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM

ZERO LATENCY PREFETCHING IN CACHES

PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE

PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM

ZERO LATENCY PREFETCHING IN CACHES

PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM

PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE

PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM

ZERO LATENCY PREFETCHING IN CACHES

USING L1 CACHE AS RE-ORDER BUFFER

USING L1 CACHE AS RE-ORDER BUFFER

Reducing Current Leakage in L1 Program Memory

Independent source read and destination write enhanced DMA