Hwa-Joon Oh

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for controlling rounding modes in single instruction multipl...
- Patent number 8,229,989
- Issue date Jul 24, 2012
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing the latency of sum-addressed shifters
- Patent number 8,166,085
- Issue date Apr 24, 2012
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed adder design for a multiply-add based floating point unit
- Patent number 8,131,795
- Issue date Mar 6, 2012
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed adder design for a multiply-add based floating point unit
- Patent number 7,490,119
- Issue date Feb 10, 2009
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for performing multi-value range checks
- Patent number 7,469,265
- Issue date Dec 23, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for controlling rounding modes in single instruction mult...
- Patent number 7,447,725
- Issue date Nov 4, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having efficient function estimate instructions
- Patent number 7,406,589
- Issue date Jul 29, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for reducing the latency of sum-addressed shif...
- Patent number 7,392,270
- Issue date Jun 24, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance implementation of exponent adjustment in a floatin...
- Patent number 7,290,023
- Issue date Oct 30, 2007
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Protecting one-hot logic against short-circuits during power-on
- Patent number 7,245,159
- Issue date Jul 17, 2007
- International Business Machines Corporation
- Sang Hoo Dhong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Leakage current reduction system and method
- Patent number 7,237,163
- Issue date Jun 26, 2007
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Byte execution unit for carrying out byte instructions in a processor
- Patent number 7,149,877
- Issue date Dec 12, 2006
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power saving in FPU with gated power based on opcodes and data
- Patent number 7,137,021
- Issue date Nov 14, 2006
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power saving in a floating point unit using a multiplier and aligne...
- Patent number 7,058,830
- Issue date Jun 6, 2006
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated logic and latch design with clock gating at static input...
- Patent number 6,914,453
- Issue date Jul 5, 2005
- International Business Machines Corporation
- Sang Hoo Dhong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Destructive read architecture for dynamic random access memories
- Patent number 6,829,682
- Issue date Dec 7, 2004
- International Business Machines Corporation
- Toshiaki Kirihata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing write operation time in dynamic r...
- Patent number 6,587,388
- Issue date Jul 1, 2003
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for cycle time reduction in a memory system us...
- Patent number 6,510,093
- Issue date Jan 21, 2003
- International Business Machines Corporation
- Sang Hoo Dhong
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
HIGH SPEED ADDER DESIGN FOR A MULTIPLY-ADD BASED FLOATING POINT UNIT
- Publication number 20090077155
- Publication date Mar 19, 2009
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Controlling Rounding Modes in Single Instruction Multi...
- Publication number 20090024684
- Publication date Jan 22, 2009
- IBM Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor Having Efficient Function Estimate Instructions
- Publication number 20080263336
- Publication date Oct 23, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus for Reducing the Latency of Sum-Addressed Shifters
- Publication number 20080195684
- Publication date Aug 14, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Byte Execution Unit for Carrying Out Byte Instructions in a Processor
- Publication number 20070061553
- Publication date Mar 15, 2007
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor having efficient function estimate instructions
- Publication number 20060259745
- Publication date Nov 16, 2006
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus for controlling rounding modes in single instruction mult...
- Publication number 20060101107
- Publication date May 11, 2006
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using a leading-sign anticipator circuit for detecting sticky-bit i...
- Publication number 20060101108
- Publication date May 11, 2006
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Leakage current reduction system and method
- Publication number 20060101315
- Publication date May 11, 2006
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Construction of a folded leading zero anticipator
- Publication number 20060053190
- Publication date Mar 9, 2006
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Alignment shifter supporting multiple precisions
- Publication number 20060031272
- Publication date Feb 9, 2006
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for reducing the latency of sum-addressed shif...
- Publication number 20060026223
- Publication date Feb 2, 2006
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Protecting one-hot logic against short-curcuits during power-on
- Publication number 20060012399
- Publication date Jan 19, 2006
- International Business Machines Corporation
- Sang Hoo Dhong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Fast operand formatting for a high performance multiply-add floatin...
- Publication number 20050228844
- Publication date Oct 13, 2005
- International Business Machines Corporation
- Sang H. Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High speed adder design for a multiply-add based floating point unit
- Publication number 20050131981
- Publication date Jun 16, 2005
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High performance implementation of exponent adjustment in a floatin...
- Publication number 20050114422
- Publication date May 26, 2005
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for performing multi-value range checks
- Publication number 20050086279
- Publication date Apr 21, 2005
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Byte execution unit for carrying out byte instructions in a processor
- Publication number 20050015576
- Publication date Jan 20, 2005
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated logic and latch design with clock gating at static input...
- Publication number 20050007152
- Publication date Jan 13, 2005
- International Business Machines Corporation
- Sang Hoo Dhong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Power saving in FPU with gated power based on opcodes and data
- Publication number 20040230849
- Publication date Nov 18, 2004
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power saving in a floating point unit using a multiplier and aligne...
- Publication number 20040186870
- Publication date Sep 23, 2004
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing write operation time in dynamic r...
- Publication number 20020159319
- Publication date Oct 31, 2002
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Application
Destructive read architecture for dynamic random access memories
- Publication number 20020161967
- Publication date Oct 31, 2002
- International Business Machines Corporation
- Toshiaki Kirihata
- G06 - COMPUTING CALCULATING COUNTING

Hwa-Joon Oh

Person

Patents Grantslast 30 patents

Method for controlling rounding modes in single instruction multipl...

Reducing the latency of sum-addressed shifters

High speed adder design for a multiply-add based floating point unit

High speed adder design for a multiply-add based floating point unit

Methods and apparatus for performing multi-value range checks

Apparatus for controlling rounding modes in single instruction mult...

Processor having efficient function estimate instructions

Apparatus and method for reducing the latency of sum-addressed shif...

High performance implementation of exponent adjustment in a floatin...

Protecting one-hot logic against short-circuits during power-on

Leakage current reduction system and method

Byte execution unit for carrying out byte instructions in a processor

Power saving in FPU with gated power based on opcodes and data

Power saving in a floating point unit using a multiplier and aligne...

Integrated logic and latch design with clock gating at static input...

Destructive read architecture for dynamic random access memories

Method and apparatus for reducing write operation time in dynamic r...

Method and apparatus for cycle time reduction in a memory system us...

Patents Applicationslast 30 patents

HIGH SPEED ADDER DESIGN FOR A MULTIPLY-ADD BASED FLOATING POINT UNIT

Method for Controlling Rounding Modes in Single Instruction Multi...

Processor Having Efficient Function Estimate Instructions

Apparatus for Reducing the Latency of Sum-Addressed Shifters

Byte Execution Unit for Carrying Out Byte Instructions in a Processor

Processor having efficient function estimate instructions

Apparatus for controlling rounding modes in single instruction mult...

Using a leading-sign anticipator circuit for detecting sticky-bit i...

Leakage current reduction system and method

Construction of a folded leading zero anticipator

Alignment shifter supporting multiple precisions

Apparatus and method for reducing the latency of sum-addressed shif...

Protecting one-hot logic against short-curcuits during power-on

Fast operand formatting for a high performance multiply-add floatin...

High speed adder design for a multiply-add based floating point unit

High performance implementation of exponent adjustment in a floatin...

Methods and apparatus for performing multi-value range checks

Byte execution unit for carrying out byte instructions in a processor

Integrated logic and latch design with clock gating at static input...

Power saving in FPU with gated power based on opcodes and data

Power saving in a floating point unit using a multiplier and aligne...

Method and apparatus for reducing write operation time in dynamic r...

Destructive read architecture for dynamic random access memories