Hyun Yi

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable device implementing fixed and floating point functiona...
- Patent number 11,137,983
- Issue date Oct 5, 2021
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable device implementing fixed and floating point functiona...
- Patent number 10,474,429
- Issue date Nov 12, 2019
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable device implementing fixed and floating point functiona...
- Patent number 9,507,565
- Issue date Nov 29, 2016
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular digital signal processing circuitry with optionally usable,...
- Patent number 8,751,551
- Issue date Jun 10, 2014
- Altera Corporation
- Keone Streicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal processing circuit blocks with support for systolic...
- Patent number 8,732,225
- Issue date May 20, 2014
- Altera Corporation
- Suleyman Demirsoy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular digital signal processing circuitry with optionally usable,...
- Patent number 8,620,977
- Issue date Dec 31, 2013
- Altera Corporation
- Keone Streicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal processing circuit blocks with support for systolic...
- Patent number 8,589,465
- Issue date Nov 19, 2013
- Altera Corporation
- Suleyman Sirri Demirsoy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular digital signal processing circuitry with optionally usable,...
- Patent number 8,549,055
- Issue date Oct 1, 2013
- Altera Corporation
- Keone Streicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal processing circuit blocks with support for systolic...
- Patent number 8,458,243
- Issue date Jun 4, 2013
- Altera Corporation
- Suleyman Sirri Demirsoy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundancy structures and methods in a programmable logic device
- Patent number 8,191,025
- Issue date May 29, 2012
- Altera Corporation
- Michael Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing calibrated on-chip termination impedance
- Patent number 8,004,308
- Issue date Aug 23, 2011
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for serially transmitting on-chip termination control si...
- Patent number 7,999,568
- Issue date Aug 16, 2011
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for providing calibrated on-chip termination impedance
- Patent number 7,884,638
- Issue date Feb 8, 2011
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable multiple supply regions with switched pass gate level...
- Patent number 7,855,574
- Issue date Dec 21, 2010
- Altera Corporation
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing calibrated on-chip termination impedance
- Patent number 7,719,309
- Issue date May 18, 2010
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Redundancy structures and methods in a programmable logic device
- Patent number 7,644,386
- Issue date Jan 5, 2010
- Altera Corporation
- Michael Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of reducing leakage current using sleep transistors in progr...
- Patent number 7,518,399
- Issue date Apr 14, 2009
- Altera Corporation
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing calibrated parallel on-chip termination im...
- Patent number 7,443,193
- Issue date Oct 28, 2008
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for providing calibrated on-chip termination impedance
- Patent number 7,423,450
- Issue date Sep 9, 2008
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for serially transmitting on-chip termination control si...
- Patent number 7,391,229
- Issue date Jun 24, 2008
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of reducing leakage current using sleep transistors in progr...
- Patent number 7,355,440
- Issue date Apr 8, 2008
- Altera Corporation
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Redundancy structures and methods in a programmable logic device
- Patent number 7,180,324
- Issue date Feb 20, 2007
- Altera Corporation
- Michael Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with redundant circuitry
- Patent number 6,965,249
- Issue date Nov 15, 2005
- Altera Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Programmable Device Implementing Fixed and Floating Point Functiona...
- Publication number 20220027128
- Publication date Jan 27, 2022
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Device Implementing Fixed and Floating Point Functiona...
- Publication number 20200026493
- Publication date Jan 23, 2020
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...
- Publication number 20140082035
- Publication date Mar 20, 2014
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...
- Publication number 20130332497
- Publication date Dec 12, 2013
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Providing Calibrated On-Chip Termination Impedance
- Publication number 20100225349
- Publication date Sep 9, 2010
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...
- Publication number 20100228806
- Publication date Sep 9, 2010
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Providing Calibrated On-Chip Termination Impedance
- Publication number 20080297193
- Publication date Dec 4, 2008
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROGRAMMABLE MULTIPLE SUPPLY REGIONS WITH SWITCHED PASS GATE LEVEL...
- Publication number 20080094105
- Publication date Apr 24, 2008
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Techniques For Providing Calibrated On-Chip Termination Impedance
- Publication number 20080061818
- Publication date Mar 13, 2008
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Redundancy structures and methods in a programmable logic device
- Publication number 20050264318
- Publication date Dec 1, 2005
- Altera Corporation
- Michael Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with redundant circuitry
- Publication number 20030072185
- Publication date Apr 17, 2003
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Programmable device implementing fixed and floating point functiona...

Programmable device implementing fixed and floating point functiona...

Programmable device implementing fixed and floating point functiona...

Modular digital signal processing circuitry with optionally usable,...

Digital signal processing circuit blocks with support for systolic...

Modular digital signal processing circuitry with optionally usable,...

Digital signal processing circuit blocks with support for systolic...

Modular digital signal processing circuitry with optionally usable,...

Digital signal processing circuit blocks with support for systolic...

Redundancy structures and methods in a programmable logic device

Techniques for providing calibrated on-chip termination impedance

Techniques for serially transmitting on-chip termination control si...

Techniques for providing calibrated on-chip termination impedance

Programmable multiple supply regions with switched pass gate level...

Techniques for providing calibrated on-chip termination impedance

Redundancy structures and methods in a programmable logic device

Method of reducing leakage current using sleep transistors in progr...

Techniques for providing calibrated parallel on-chip termination im...

Techniques for providing calibrated on-chip termination impedance

Techniques for serially transmitting on-chip termination control si...

Method of reducing leakage current using sleep transistors in progr...

Redundancy structures and methods in a programmable logic device

Programmable logic device with redundant circuitry

Patents Applicationslast 30 patents

Programmable Device Implementing Fixed and Floating Point Functiona...

Programmable Device Implementing Fixed and Floating Point Functiona...

MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...

MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...

Techniques for Providing Calibrated On-Chip Termination Impedance

MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...

Techniques for Providing Calibrated On-Chip Termination Impedance

PROGRAMMABLE MULTIPLE SUPPLY REGIONS WITH SWITCHED PASS GATE LEVEL...

Techniques For Providing Calibrated On-Chip Termination Impedance

Redundancy structures and methods in a programmable logic device

Programmable logic device with redundant circuitry