Ian MacPherson Flanagan

Follow

Person

Minneapolis, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Delay-locked loop with built-in self-test of phase margin
- Patent number 7,042,971
- Issue date May 9, 2006
- LSI Logic Corporation
- Ian M. Flanagan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System for measuring phase error between two clocks by using a plur...
- Patent number 6,636,979
- Issue date Oct 21, 2003
- LSI Logic Corporation
- Dayanand K. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked loop with built-in self-test of phase margin and loop...
- Patent number 6,262,634
- Issue date Jul 17, 2001
- LSI Logic Corporation
- Ian MacPherson Flanagan
- H03 - BASIC ELECTRONIC CIRCUITRY