Ian Shaeffer

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Buffer IC with asymmetric memory module interfaces
- Patent number 12,189,548
- Issue date Jan 7, 2025
- RAMBUS INC.
- Ian P. Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deferred fractional memory row activation
- Patent number 12,190,990
- Issue date Jan 7, 2025
- RAMBUS INC.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Grant
Folded memory modules
- Patent number 12,147,367
- Issue date Nov 19, 2024
- RAMBUS INC.
- Amir Amirkhany
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device comprising programmable command-and-address and/or da...
- Patent number 12,142,348
- Issue date Nov 12, 2024
- RAMBUS INC.
- Ian Shaeffer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for calibrating write timing in a memory system
- Patent number 12,136,452
- Issue date Nov 5, 2024
- RAMBUS INC.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock generation for timing communications with ranks of memory dev...
- Patent number 12,066,958
- Issue date Aug 20, 2024
- RAMBUS INC.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die termination of address and command signals
- Patent number 12,002,540
- Issue date Jun 4, 2024
- RAMBUS INC.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Command-triggered data clock distribution mode
- Patent number 11,955,161
- Issue date Apr 9, 2024
- RAMBUS INC.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access during memory calibration
- Patent number 11,947,468
- Issue date Apr 2, 2024
- RAMBUS INC.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory error detection
- Patent number 11,928,020
- Issue date Mar 12, 2024
- RAMBUS INC.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with staggered request signal output
- Patent number 11,830,573
- Issue date Nov 28, 2023
- RAMBUS INC.
- Ian P. Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Protocol including a command-specified timing reference signal
- Patent number 11,816,047
- Issue date Nov 14, 2023
- RAMBUS INC.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with deferred fractional row activation
- Patent number 11,804,250
- Issue date Oct 31, 2023
- RAMBUS INC.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Grant
Strobe acquisition and tracking
- Patent number 11,790,962
- Issue date Oct 17, 2023
- RAMBUS INC.
- Bret Stott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device comprising programmable command-and-address and/or da...
- Patent number 11,783,879
- Issue date Oct 10, 2023
- RAMBUS INC.
- Ian Shaeffer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory module with configurable command buffer
- Patent number 11,782,863
- Issue date Oct 10, 2023
- RAMBUS INC.
- Liji Gopalakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Folded memory modules
- Patent number 11,755,521
- Issue date Sep 12, 2023
- RAMBUS INC.
- Amir Amirkhany
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die termination
- Patent number 11,742,855
- Issue date Aug 29, 2023
- RAMBUS INC.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Interface bus resource allocation
- Patent number 11,741,041
- Issue date Aug 29, 2023
- Apple Inc.
- Ian P. Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system topologies including a memory die stack
- Patent number 11,727,982
- Issue date Aug 15, 2023
- RAMBUS INC.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die termination of address and command signals
- Patent number 11,688,441
- Issue date Jun 27, 2023
- RAMBUS INC.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for calibrating write timing in a memory system
- Patent number 11,682,448
- Issue date Jun 20, 2023
- RAMBUS INC.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fractional program commands for memory devices
- Patent number 11,651,823
- Issue date May 16, 2023
- RAMBUS INC.
- Brent S. Haukness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer console for throttling the video bitrate of video streams...
- Patent number 11,636,801
- Issue date Apr 25, 2023
- Apple Inc.
- Reese A. Schreiber
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Clock generation for timing communications with ranks of memory dev...
- Patent number 11,630,788
- Issue date Apr 18, 2023
- RAMBUS INC.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command-triggered data clock distribution
- Patent number 11,587,605
- Issue date Feb 21, 2023
- RAMBUS INC.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory error detection
- Patent number 11,579,965
- Issue date Feb 14, 2023
- RAMBUS INC.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access during memory calibration
- Patent number 11,474,957
- Issue date Oct 18, 2022
- RAMBUS INC.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die termination of address and command signals
- Patent number 11,468,928
- Issue date Oct 11, 2022
- RAMBUS INC.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Folded memory modules
- Patent number 11,409,682
- Issue date Aug 9, 2022
- RAMBUS INC.
- Amir Amirkhany
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Clock Generation for Timing Communications with Ranks of Memory Dev...
- Publication number 20250053524
- Publication date Feb 13, 2025
- Rambus Inc.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-Die Termination of Address and Command Signals
- Publication number 20250037746
- Publication date Jan 30, 2025
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Access During Memory Calibration
- Publication number 20240330207
- Publication date Oct 3, 2024
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory error detection
- Publication number 20240296088
- Publication date Sep 5, 2024
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT
- Publication number 20240282357
- Publication date Aug 22, 2024
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
- Publication number 20240177747
- Publication date May 30, 2024
- Rambus Inc.
- Ian P. Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Protocol including selective output by memory of a timing reference...
- Publication number 20240160588
- Publication date May 16, 2024
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-Die Termination of Address and Command Signals
- Publication number 20240105242
- Publication date Mar 28, 2024
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DA...
- Publication number 20240096387
- Publication date Mar 21, 2024
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION
- Publication number 20240062788
- Publication date Feb 22, 2024
- Rambus Inc.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Application
On-Die Termination
- Publication number 20240039536
- Publication date Feb 1, 2024
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
FOLDED MEMORY MODULES
- Publication number 20240020258
- Publication date Jan 18, 2024
- Rambus Inc.
- AMIR AMIRKHANY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM
- Publication number 20230410880
- Publication date Dec 21, 2023
- Rambus Inc.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Generation for Timing Communications with Ranks of Memory Dev...
- Publication number 20230359572
- Publication date Nov 9, 2023
- Rambus Inc.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Error Detection
- Publication number 20230333927
- Publication date Oct 19, 2023
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT
- Publication number 20230326513
- Publication date Oct 12, 2023
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Access During Memory Calibration
- Publication number 20230100348
- Publication date Mar 30, 2023
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-Die Termination of Address and Command Signals
- Publication number 20230016728
- Publication date Jan 19, 2023
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
FOLDED MEMORY MODULES
- Publication number 20220398206
- Publication date Dec 15, 2022
- Rambus Inc.
- AMIR AMIRKHANY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH ALTERNATIVE COMMAND INTERFACES
- Publication number 20220374381
- Publication date Nov 24, 2022
- Rambus Inc.
- Liji Gopalakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM
- Publication number 20220366960
- Publication date Nov 17, 2022
- Rambus Inc.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
- Publication number 20220343956
- Publication date Oct 27, 2022
- Rambus Inc.
- Ian P. Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT THAT APPLIES DIFFERENT DATA INTERFACE TERMINATIO...
- Publication number 20220345131
- Publication date Oct 27, 2022
- Rambus Inc.
- Kyung Suk Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory System Topologies Including A Memory Die Stack
- Publication number 20220336008
- Publication date Oct 20, 2022
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interface Bus Resource Allocation
- Publication number 20220269640
- Publication date Aug 25, 2022
- Apple Inc.
- Ian P. Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION
- Publication number 20220262412
- Publication date Aug 18, 2022
- Rambus Inc.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DA...
- Publication number 20220172760
- Publication date Jun 2, 2022
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
ASYMMETRIC-CHANNEL MEMORY SYSTEM
- Publication number 20220147472
- Publication date May 12, 2022
- Rambus Inc.
- Ian P. Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-Die Termination
- Publication number 20220140828
- Publication date May 5, 2022
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Error Detection
- Publication number 20220138042
- Publication date May 5, 2022
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING

Ian Shaeffer

Person

Patents Grantslast 30 patents

Buffer IC with asymmetric memory module interfaces

Deferred fractional memory row activation

Folded memory modules

Memory device comprising programmable command-and-address and/or da...

Method and apparatus for calibrating write timing in a memory system

Clock generation for timing communications with ranks of memory dev...

On-die termination of address and command signals

Command-triggered data clock distribution mode

Memory access during memory calibration

Memory error detection

Memory controller with staggered request signal output

Protocol including a command-specified timing reference signal

Memory with deferred fractional row activation

Strobe acquisition and tracking

Memory device comprising programmable command-and-address and/or da...

Memory module with configurable command buffer

Folded memory modules

On-die termination

Interface bus resource allocation

Memory system topologies including a memory die stack

On-die termination of address and command signals

Method and apparatus for calibrating write timing in a memory system

Fractional program commands for memory devices

Computer console for throttling the video bitrate of video streams...

Clock generation for timing communications with ranks of memory dev...

Command-triggered data clock distribution

Memory error detection

Memory access during memory calibration

On-die termination of address and command signals

Folded memory modules

Patents Applicationslast 30 patents

Clock Generation for Timing Communications with Ranks of Memory Dev...

On-Die Termination of Address and Command Signals

Memory Access During Memory Calibration

Memory error detection

MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT

MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT

Protocol including selective output by memory of a timing reference...

On-Die Termination of Address and Command Signals

MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DA...

MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION

On-Die Termination

FOLDED MEMORY MODULES

METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

Clock Generation for Timing Communications with Ranks of Memory Dev...

Memory Error Detection

MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT

Memory Access During Memory Calibration

On-Die Termination of Address and Command Signals

FOLDED MEMORY MODULES

MEMORY WITH ALTERNATIVE COMMAND INTERFACES

METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT

INTEGRATED CIRCUIT THAT APPLIES DIFFERENT DATA INTERFACE TERMINATIO...

Memory System Topologies Including A Memory Die Stack

Interface Bus Resource Allocation

MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION

MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DA...

ASYMMETRIC-CHANNEL MEMORY SYSTEM

On-Die Termination

Memory Error Detection