Ibrahim A. Ouda

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Implementing lane shuffle for fault-tolerant communication links
- Patent number 8,792,332
- Issue date Jul 29, 2014
- International Business Machines Corporation
- Ryan Abel Heckendorf
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Handling concurrent address translation cache misses and hits under...
- Patent number 7,539,840
- Issue date May 26, 2009
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
VARIABLE LATENCY MEMORY DELAY IMPLEMENTATION
- Publication number 20130185477
- Publication date Jul 18, 2013
- International Business Machines Corporation
- Victor A. Acuña
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFYING DATA RECEIVED OUT-OF-ORDER FROM A BUS
- Publication number 20130159591
- Publication date Jun 20, 2013
- International Business Machines Corporation
- Victor A. Acuña
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HANDLING CONCURRENT ADDRESS TRANSLATION CACHE MISSES AND HITS UNDER...
- Publication number 20090187695
- Publication date Jul 23, 2009
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Handling Concurrent Address Translation Ca...
- Publication number 20070283121
- Publication date Dec 6, 2007
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for command list ordering after multiple cache misses
- Publication number 20070180158
- Publication date Aug 2, 2007
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for cache hit under miss collision handling
- Publication number 20070180157
- Publication date Aug 2, 2007
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I/O address translation blocking in a secure system during power-on...
- Publication number 20070180269
- Publication date Aug 2, 2007
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for completing IO commands after an IO translation miss
- Publication number 20070180156
- Publication date Aug 2, 2007
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for aligning data
- Publication number 20070006009
- Publication date Jan 4, 2007
- International Business Machines Corporation
- Scott Douglas Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for allocating memory
- Publication number 20050071595
- Publication date Mar 31, 2005
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and hardware apparatus for implementing frame alteration com...
- Publication number 20040258057
- Publication date Dec 23, 2004
- International Business Machines Corporation
- John David Irish
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for implementing actions based on packet class...
- Publication number 20040258067
- Publication date Dec 23, 2004
- INTERNATIONAL BUSSINESS MACHINES CORPORATION
- John David Irish
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methods and apparatus for routing packets
- Publication number 20040246960
- Publication date Dec 9, 2004
- International Business Machines Corporation
- John David Irish
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Ibrahim A. Ouda

Person

Patents Grantslast 30 patents

Implementing lane shuffle for fault-tolerant communication links

Handling concurrent address translation cache misses and hits under...

Patents Applicationslast 30 patents

VARIABLE LATENCY MEMORY DELAY IMPLEMENTATION

VERIFYING DATA RECEIVED OUT-OF-ORDER FROM A BUS

HANDLING CONCURRENT ADDRESS TRANSLATION CACHE MISSES AND HITS UNDER...

Method and Apparatus for Handling Concurrent Address Translation Ca...

Method for command list ordering after multiple cache misses

Method for cache hit under miss collision handling

I/O address translation blocking in a secure system during power-on...

Method for completing IO commands after an IO translation miss

Methods and apparatus for aligning data

Methods and apparatus for allocating memory

Method and hardware apparatus for implementing frame alteration com...

Method and apparatus for implementing actions based on packet class...

Methods and apparatus for routing packets