Ignazio Antonino Urzi

Person

Voreppe, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Method and device for managing operation of a computing unit capabl...
- Patent number 11,614,949
- Issue date Mar 28, 2023
- STMicroelectronics (Grenoble 2) SAS
- Loic Pallardy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus use with interrupts
- Patent number 10,255,207
- Issue date Apr 9, 2019
- STMicroelectronics (Research & Development) Limited
- Davide Sarta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of handling transactions, corresponding system and computer...
- Patent number 10,102,171
- Issue date Oct 16, 2018
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for designing network on chip interconnect arrangements
- Patent number 10,019,399
- Issue date Jul 10, 2018
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of handling transactions, corresponding system and computer...
- Patent number 9,697,161
- Issue date Jul 4, 2017
- STMicroelectronics (Grenoble) SAS
- Daniele Mangano
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory encryption method compatible with a memory interleaved syste...
- Patent number 9,419,952
- Issue date Aug 16, 2016
- STMicroelectronics (Grenoble 2) SAS
- Ignazio Antonino Urzi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Debug system, and related integrated circuit and method
- Patent number 9,389,979
- Issue date Jul 12, 2016
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for designing network on chip interconnect arrangements
- Patent number 9,202,002
- Issue date Dec 1, 2015
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Arrangement and method
- Patent number 9,178,776
- Issue date Nov 3, 2015
- STMicroelectronics (Grenoble 2) SAS
- Ignazio Antonino Urzi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Control device, for instance for systems-on-chip, and corresponding...
- Patent number 9,100,354
- Issue date Aug 4, 2015
- STMicroelectronics S.R.L.
- Daniele Mangano
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interface system, and corresponding integrated circuit and method
- Patent number 9,026,761
- Issue date May 5, 2015
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communications arrangement for a system in package
- Patent number 8,873,668
- Issue date Oct 28, 2014
- STMicroelectronics S.A.
- Andrew Ferris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for switching clock frequency in a system-in-p...
- Patent number 8,831,160
- Issue date Sep 9, 2014
- STMicroelectronics (Research & Development) Limited
- Andrew Ferris
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for routing transactions through partitions of...
- Patent number 8,782,302
- Issue date Jul 15, 2014
- STMicroelectronics (Grenoble 2) SAS
- Ignazio Antonino Urzi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communication system, and corresponding integrated circuit and method
- Patent number 8,780,935
- Issue date Jul 15, 2014
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction reordering system and method with protocol indifference
- Patent number 8,677,045
- Issue date Mar 18, 2014
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communication system and corresponding integrated circuit and method
- Patent number 8,630,181
- Issue date Jan 14, 2014
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interconnection method and device, for example for systems-on-chip
- Patent number 8,631,184
- Issue date Jan 14, 2014
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communication system and method
- Patent number 8,576,879
- Issue date Nov 5, 2013
- STMicroelectronics (Grenoble 2) SAS
- Alberto Scandurra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Connection arrangement
- Patent number 8,571,016
- Issue date Oct 29, 2013
- STMicroelectronics (R&D) Ltd.
- Ignazio Urzi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for interfacing multiple dies with mapping to...
- Patent number 8,521,937
- Issue date Aug 27, 2013
- STMicroelectronics (Grenoble 2) SAS
- Ignazio Antonino Urzi
- A01 - AGRICULTURE FORESTRY ANIMAL HUSBANDRY HUNTING TRAPPING FISHING
Information Patent Grant
Method and apparatus for interfacing multiple dies with mapping for...
- Patent number 8,347,258
- Issue date Jan 1, 2013
- STMicroelectronics (Grenoble 2) SAS
- Ignazio Antonino Urzi
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND DEVICE FOR MANAGING OPERATION OF A COMPUTING UNIT CAPABL...
- Publication number 20200394047
- Publication date Dec 17, 2020
- STMicroelectronics (Grand Ouest) SAS
- Loic Pallardy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF HANDLING TRANSACTIONS, CORRESPONDING SYSTEM AND COMPUTER...
- Publication number 20170270070
- Publication date Sep 21, 2017
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR DESIGNING NETWORK ON CHIP INTERCONNECT ARRANGEMENTS
- Publication number 20160070667
- Publication date Mar 10, 2016
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ENCRYPTION METHOD COMPATIBLE WITH A MEMORY INTERLEAVED SYSTE...
- Publication number 20150358300
- Publication date Dec 10, 2015
- STMicroelectronics (Grenoble 2) SAS
- Ignazio Antonino URZI
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS USE WITH INTERRUPTS
- Publication number 20150127865
- Publication date May 7, 2015
- STMicroelectronics (Research and Development) Limited
- Davide Sarta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR DESIGNING NETWORK ON CHIP INTERCONNECT ARRANGEMENTS
- Publication number 20150106778
- Publication date Apr 16, 2015
- STMicroelectronics (Grenoble 2) SAS
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF HANDLING TRANSACTIONS, CORRESPONDING SYSTEM AND COMPUTER...
- Publication number 20140289439
- Publication date Sep 25, 2014
- STMicroelectronics S.r. I.
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOSED LOOP END-TO-END QOS ON-CHIP ARCHITECTURE
- Publication number 20140112149
- Publication date Apr 24, 2014
- STMicroelectronics (Grenoble 2) SAS
- Ignazio Antonino Urzi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG SYSTEM, AND RELATED INTEGRATED CIRCUIT AND METHOD
- Publication number 20140095932
- Publication date Apr 3, 2014
- STMicroelectronics S.r. I.
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARRANGEMENT AND METHOD
- Publication number 20130268990
- Publication date Oct 10, 2013
- STMicroelectronics S.r. I.
- Ignazio Antonino Urzi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR SWITCHING CLOCK FREQUENCY IN A SYSTEM-IN-P...
- Publication number 20130195235
- Publication date Aug 1, 2013
- STMicroelectronics (Grenoble 2) SAS
- Andrew FERRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROL DEVICE, FOR INSTANCE FOR SYSTEMS-ON-CHIP, AND CORRESPONDING...
- Publication number 20130163615
- Publication date Jun 27, 2013
- STMICROELECTRONICS (GRENOBLE2) SAS
- Daniele Mangano
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
COMMUNICATIONS ARRANGEMENT FOR A SYSTEM IN PACKAGE
- Publication number 20130142227
- Publication date Jun 6, 2013
- STMicroelectronics S.A.
- Andrew FERRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE COMMUNICATIONS
- Publication number 20130103865
- Publication date Apr 25, 2013
- Ignazio Antonino Urzi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERSATILE DATA PROCESSOR EMBEDDED IN A MEMORY CONTROLLER
- Publication number 20130061016
- Publication date Mar 7, 2013
- STMicroelectronics, (Grenoble2) SAS
- Ignazio Antonino Urzi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATION SYSTEM AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD
- Publication number 20120281713
- Publication date Nov 8, 2012
- STMicroelectronics S.r.l.
- Daniele MANGANO
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR INTERFACING MULTIPLE DIES WITH MAPPING FOR...
- Publication number 20120210288
- Publication date Aug 16, 2012
- STMicroelectronics (Research and Development) Limited
- Ignazio Antonino URZI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR INTERFACING MULTIPLE DIES WITH MAPPING TO...
- Publication number 20120210093
- Publication date Aug 16, 2012
- STMicroelectronics (Research & Develoment) Limited
- Ignazio Antonino URZI
- A01 - AGRICULTURE FORESTRY ANIMAL HUSBANDRY HUNTING TRAPPING FISHING
Information Patent Application
INTERFACE SYSTEM, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD
- Publication number 20120159095
- Publication date Jun 21, 2012
- STMicroelectronics S.r.l
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATION SYSTEM, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD
- Publication number 20120155489
- Publication date Jun 21, 2012
- STMicroelectronics S.r.l
- Daniele MANGANO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ROUTING TRANSACTIONS THROUGH PARTITIONS OF...
- Publication number 20120159017
- Publication date Jun 21, 2012
- STMICROELECTRONICS S.R.L.
- Ignazio Antonino URZI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSACTION REORDERING ARRANGEMENT
- Publication number 20120079154
- Publication date Mar 29, 2012
- STMICROELECTRONICS S.R.L.
- Daniele MANGANO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REORDERING ARRANGEMENT
- Publication number 20120079148
- Publication date Mar 29, 2012
- STMICROELECTRONICS S.R.L.
- Ignazio Antonino URZI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONNECTION ARRANGEMENT
- Publication number 20120008620
- Publication date Jan 12, 2012
- STMICROELECTRONICS (R&D) LTD
- Ignazio Urzi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE AND A PACKAGE COMPRISING A PLURALITY OF DIES
- Publication number 20120001668
- Publication date Jan 5, 2012
- STMicroelectronics (Grenoble 2) SAS
- Ignazio Antonino Urzi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATION SYSTEM AND METHOD
- Publication number 20110320669
- Publication date Dec 29, 2011
- STMicroelectronics S.r.l.
- Alberto Scandurra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECTION METHOD AND DEVICE, FOR EXAMPLE FOR SYSTEMS-ON-CHIP
- Publication number 20110289253
- Publication date Nov 24, 2011
- STMicroelectronics S.r.l.
- Daniele Mangano
- G06 - COMPUTING CALCULATING COUNTING

Ignazio Antonino Urzi

Person

Patents Grantslast 30 patents

Method and device for managing operation of a computing unit capabl...

Method and apparatus use with interrupts

Method of handling transactions, corresponding system and computer...

System for designing network on chip interconnect arrangements

Method of handling transactions, corresponding system and computer...

Memory encryption method compatible with a memory interleaved syste...

Debug system, and related integrated circuit and method

System for designing network on chip interconnect arrangements

Arrangement and method

Control device, for instance for systems-on-chip, and corresponding...

Interface system, and corresponding integrated circuit and method

Communications arrangement for a system in package

Method and apparatus for switching clock frequency in a system-in-p...

Method and apparatus for routing transactions through partitions of...

Communication system, and corresponding integrated circuit and method

Transaction reordering system and method with protocol indifference

Communication system and corresponding integrated circuit and method

Interconnection method and device, for example for systems-on-chip

Communication system and method

Connection arrangement

Method and apparatus for interfacing multiple dies with mapping to...

Method and apparatus for interfacing multiple dies with mapping for...

Patents Applicationslast 30 patents

METHOD AND DEVICE FOR MANAGING OPERATION OF A COMPUTING UNIT CAPABL...

METHOD OF HANDLING TRANSACTIONS, CORRESPONDING SYSTEM AND COMPUTER...

SYSTEM FOR DESIGNING NETWORK ON CHIP INTERCONNECT ARRANGEMENTS

MEMORY ENCRYPTION METHOD COMPATIBLE WITH A MEMORY INTERLEAVED SYSTE...

METHOD AND APPARATUS USE WITH INTERRUPTS

SYSTEM FOR DESIGNING NETWORK ON CHIP INTERCONNECT ARRANGEMENTS

METHOD OF HANDLING TRANSACTIONS, CORRESPONDING SYSTEM AND COMPUTER...

CLOSED LOOP END-TO-END QOS ON-CHIP ARCHITECTURE

DEBUG SYSTEM, AND RELATED INTEGRATED CIRCUIT AND METHOD

ARRANGEMENT AND METHOD

METHOD AND APPARATUS FOR SWITCHING CLOCK FREQUENCY IN A SYSTEM-IN-P...

CONTROL DEVICE, FOR INSTANCE FOR SYSTEMS-ON-CHIP, AND CORRESPONDING...

COMMUNICATIONS ARRANGEMENT FOR A SYSTEM IN PACKAGE

FLEXIBLE COMMUNICATIONS

VERSATILE DATA PROCESSOR EMBEDDED IN A MEMORY CONTROLLER

COMMUNICATION SYSTEM AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD

METHOD AND APPARATUS FOR INTERFACING MULTIPLE DIES WITH MAPPING FOR...

METHOD AND APPARATUS FOR INTERFACING MULTIPLE DIES WITH MAPPING TO...

INTERFACE SYSTEM, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD

COMMUNICATION SYSTEM, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD

METHOD AND APPARATUS FOR ROUTING TRANSACTIONS THROUGH PARTITIONS OF...

TRANSACTION REORDERING ARRANGEMENT

REORDERING ARRANGEMENT

CONNECTION ARRANGEMENT

DIE AND A PACKAGE COMPRISING A PLURALITY OF DIES

COMMUNICATION SYSTEM AND METHOD

INTERCONNECTION METHOD AND DEVICE, FOR EXAMPLE FOR SYSTEMS-ON-CHIP