Igor Keller

Person

Pleasanton, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit design modification using timing-based yield calculation
- Patent number 12,086,529
- Issue date Sep 10, 2024
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell instance charge model for delay calculation
- Patent number 11,775,719
- Issue date Oct 3, 2023
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and product for deferred merge based method for gra...
- Patent number 11,188,696
- Issue date Nov 30, 2021
- Cadence Design Systems, Inc.
- Amit Dhuria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and computer program product for characterizing t...
- Patent number 11,023,640
- Issue date Jun 1, 2021
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and computer program product for characterizing a...
- Patent number 11,023,636
- Issue date Jun 1, 2021
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analyzing clock jitter using delay calculation engine
- Patent number 10,963,610
- Issue date Mar 30, 2021
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Characterizing electronic component parameters including on-chip va...
- Patent number 10,789,406
- Issue date Sep 29, 2020
- Cadence Design Systems, Inc.
- Shiva Raja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for yield calculation using statistical timing...
- Patent number 10,430,536
- Issue date Oct 1, 2019
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay propagation for multiple logic cells using correlation and co...
- Patent number 10,275,554
- Issue date Apr 30, 2019
- Cadence Design Systems, Inc.
- Mikhail Chetin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo-inverter configuration for signal electromigration analysis
- Patent number 10,192,012
- Issue date Jan 29, 2019
- Jalal Wehbeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for statistical static timing analysis
- Patent number 10,185,795
- Issue date Jan 22, 2019
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for statistical static timing analysis
- Patent number 10,073,934
- Issue date Sep 11, 2018
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for accurate modeling of back-miller effect in ti...
- Patent number 9,928,324
- Issue date Mar 27, 2018
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for timing analysis with adaptive timing window o...
- Patent number 9,881,123
- Issue date Jan 30, 2018
- Cadence Design Systems, Inc.
- Ratnakar Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and articles of manufacture for enhancing timing...
- Patent number 9,710,593
- Issue date Jul 18, 2017
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using waveform propagation for accurate delay calculation
- Patent number 9,582,626
- Issue date Feb 28, 2017
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
View data sharing for efficient multi-mode multi-corner timing anal...
- Patent number 9,384,310
- Issue date Jul 5, 2016
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static timing analysis of integrated circuit designs with flexible...
- Patent number 9,129,078
- Issue date Sep 8, 2015
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lumped aggressor model for signal integrity timing analysis
- Patent number 9,003,342
- Issue date Apr 7, 2015
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static timing analysis methods for integrated circuit designs using...
- Patent number 8,966,421
- Issue date Feb 24, 2015
- Cadence Design Systems, Inc.
- Vinod Kariat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for comprehension of common path pessimism dur...
- Patent number 8,938,703
- Issue date Jan 20, 2015
- Cadence Design Systems, Inc.
- Sneh Saurabh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constructing equivalent waveform models for static timing analysis...
- Patent number 8,924,905
- Issue date Dec 30, 2014
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Waveform based variational static timing analysis
- Patent number 8,782,583
- Issue date Jul 15, 2014
- Cadence Design Systems, Inc.
- Saurabh K. Tiwary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating an equivalent waveform model in static timing analysis
- Patent number 8,726,211
- Issue date May 13, 2014
- Cadence Design Systems, Inc.
- Joel R. Phillips
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and apparatus for timing and signal integrity ana...
- Patent number 8,631,369
- Issue date Jan 14, 2014
- Cadence Design Systems, Inc.
- Vinod Kariat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for compact modeling of circuit stages for static timing an...
- Patent number 8,615,725
- Issue date Dec 24, 2013
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Equivalent waveform model for static timing analysis of integrated...
- Patent number 8,601,420
- Issue date Dec 3, 2013
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible noise and delay modeling of circuit stages for static timi...
- Patent number 8,595,669
- Issue date Nov 26, 2013
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent noise and delay modeling of circuit stages for static ti...
- Patent number 8,543,954
- Issue date Sep 24, 2013
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-CCC current source models and static timing analysis methods...
- Patent number 8,533,644
- Issue date Sep 10, 2013
- Cadence Design Systems, Inc.
- Vinod Kariat
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EFFICIENT DELAY CALCULATIONS IN REPLICATED DESIGNS
- Publication number 20240143877
- Publication date May 2, 2024
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATING AN EQUIVALENT WAVEFORM MODEL IN STATIC TIMING ANALYSIS
- Publication number 20140096099
- Publication date Apr 3, 2014
- Cadence Design Systems, Inc.
- Joel R. Phillips
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR THERMAL ANALYSIS
- Publication number 20090199140
- Publication date Aug 6, 2009
- Vinod Kariat
- G06 - COMPUTING CALCULATING COUNTING

Igor Keller

Person

Patents Grantslast 30 patents

Circuit design modification using timing-based yield calculation

Cell instance charge model for delay calculation

Method, system, and product for deferred merge based method for gra...

Methods, systems, and computer program product for characterizing t...

Methods, systems, and computer program product for characterizing a...

Analyzing clock jitter using delay calculation engine

Characterizing electronic component parameters including on-chip va...

Method and apparatus for yield calculation using statistical timing...

Delay propagation for multiple logic cells using correlation and co...

Pseudo-inverter configuration for signal electromigration analysis

Systems and methods for statistical static timing analysis

Systems and methods for statistical static timing analysis

System and method for accurate modeling of back-miller effect in ti...

Method and system for timing analysis with adaptive timing window o...

Methods, systems, and articles of manufacture for enhancing timing...

Using waveform propagation for accurate delay calculation

View data sharing for efficient multi-mode multi-corner timing anal...

Static timing analysis of integrated circuit designs with flexible...

Lumped aggressor model for signal integrity timing analysis

Static timing analysis methods for integrated circuit designs using...

Method and apparatus for comprehension of common path pessimism dur...

Constructing equivalent waveform models for static timing analysis...

Waveform based variational static timing analysis

Generating an equivalent waveform model in static timing analysis

Methods, systems, and apparatus for timing and signal integrity ana...

Methods for compact modeling of circuit stages for static timing an...

Equivalent waveform model for static timing analysis of integrated...

Flexible noise and delay modeling of circuit stages for static timi...

Concurrent noise and delay modeling of circuit stages for static ti...

Multi-CCC current source models and static timing analysis methods...

Patents Applicationslast 30 patents

EFFICIENT DELAY CALCULATIONS IN REPLICATED DESIGNS

GENERATING AN EQUIVALENT WAVEFORM MODEL IN STATIC TIMING ANALYSIS

METHOD AND APPARATUS FOR THERMAL ANALYSIS