IGOR V. PEIDOUS

Person

Loudonville, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit employing variable thickness film
- Patent number 9,640,666
- Issue date May 2, 2017
- GLOBALFOUNDRIES, INC.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a metal silicide region in an integrated circuit
- Patent number 8,987,102
- Issue date Mar 24, 2015
- Applied Materials, Inc.
- Michael G. Ward
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods to adjust threshold voltage in semiconductor devices
- Patent number 8,802,522
- Issue date Aug 12, 2014
- Applied Materials, Inc.
- Michael G. Ward
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating interconnect structures for semiconductor de...
- Patent number 8,143,138
- Issue date Mar 27, 2012
- Applied Materials, Inc.
- Ryan James Patz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor having a channel with tensile strain and oriented along...
- Patent number 8,039,878
- Issue date Oct 18, 2011
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating a stressed MOS device
- Patent number 7,902,008
- Issue date Mar 8, 2011
- GLOBALFOUNDRIES Inc.
- Igor Peidous
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Stress enhanced transistor
- Patent number 7,893,496
- Issue date Feb 22, 2011
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor having a channel with tensile strain and oriented along...
- Patent number 7,767,540
- Issue date Aug 3, 2010
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating low contact resistance CMOS circuits
- Patent number 7,754,554
- Issue date Jul 13, 2010
- GLOBALFOUNDRIES Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress enhanced transistor and methods for its fabrication
- Patent number 7,704,840
- Issue date Apr 27, 2010
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stressed MOS device
- Patent number 7,696,534
- Issue date Apr 13, 2010
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating dual material gate in a semiconductor device
- Patent number 7,635,648
- Issue date Dec 22, 2009
- Applied Materials, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistors and methods for fabricating the same
- Patent number 7,605,045
- Issue date Oct 20, 2009
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress enhanced MOS transistor and methods for its fabrication
- Patent number 7,534,689
- Issue date May 19, 2009
- Advanced Micro Devices, Inc.
- Rohit Pal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structures including multiple crystallographic orient...
- Patent number 7,494,918
- Issue date Feb 24, 2009
- International Business Machines Corporation
- Byeong Y. Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating a stressed MOS device
- Patent number 7,462,524
- Issue date Dec 9, 2008
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stressed MOS device and methods for its fabrication
- Patent number 7,456,058
- Issue date Nov 25, 2008
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating semiconductor substrates with silicon regio...
- Patent number 7,432,174
- Issue date Oct 7, 2008
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stressed MOS device and method for its fabrication
- Patent number 7,410,859
- Issue date Aug 12, 2008
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating a CMOS device including silicide contacts
- Patent number 7,348,233
- Issue date Mar 25, 2008
- Advanced Micro Devices, Inc.
- Martin Gerhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabrication of a stressed MOS device
- Patent number 7,326,601
- Issue date Feb 5, 2008
- Advanced Micro Devices, Inc.
- Frank Wirbeleit
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHODS FOR FILLING HIGH ASPECT RATIO FEATURES ON SUBSTRATES
- Publication number 20130288465
- Publication date Oct 31, 2013
- Applied Materials, Inc.
- IGOR PEIDOUS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING A METAL SILICIDE REGION IN AN INTEGRATED CIRCUIT
- Publication number 20130026617
- Publication date Jan 31, 2013
- Applied Materials, Inc.
- MICHAEL G. WARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS TO ADJUST THRESHOLD VOLTAGE IN SEMICONDUCTOR DEVICES
- Publication number 20120171855
- Publication date Jul 5, 2012
- Applied Materials, Inc.
- MICHAEL G. WARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR HAVING A CHANNEL WITH TENSILE STRAIN AND ORIENTED ALONG...
- Publication number 20100252866
- Publication date Oct 7, 2010
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS ENHANCED TRANSISTOR
- Publication number 20100096698
- Publication date Apr 22, 2010
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DE...
- Publication number 20100078825
- Publication date Apr 1, 2010
- Ryan James Patz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING DUAL MATERIAL GATE IN A SEMICONDUCTOR DEVICE
- Publication number 20090258484
- Publication date Oct 15, 2009
- IGOR PEIDOUS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESSED MOS DEVICE AND METHODS FOR ITS FABRICATION
- Publication number 20090050963
- Publication date Feb 26, 2009
- Advanced Micro Devices, Inc.
- Igor PEIDOUS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT EMPLOYING VARIABLE THICKNESS FILM
- Publication number 20090026545
- Publication date Jan 29, 2009
- Advanced Micro Devices, Inc.
- Igor PEIDOUS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESSED MOS DEVICE
- Publication number 20080258175
- Publication date Oct 23, 2008
- Advanced Micro Devices, Inc.
- Igor PEIDOUS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING SEMICONDUCTOR SUBSTRATES WITH SILICON REGIO...
- Publication number 20080242014
- Publication date Oct 2, 2008
- Advanced Micro Devices, Inc.
- Igor PEIDOUS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING LOW CONTACT RESISTANCE CMOS CIRCUITS
- Publication number 20080182370
- Publication date Jul 31, 2008
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS ENHANCED TRANSISTOR AND METHODS FOR ITS FABRICATION
- Publication number 20080142835
- Publication date Jun 19, 2008
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION
- Publication number 20080119031
- Publication date May 22, 2008
- Rohit Pal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURES INCLUDING MULTIPLE CRYSTALLOGRAPHIC ORIENT...
- Publication number 20080083952
- Publication date Apr 10, 2008
- International Business Machines Corporation
- Byeong Y. Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD EFFECT TRANSISTORS AND METHODS FOR FABRICATING THE SAME
- Publication number 20080014704
- Publication date Jan 17, 2008
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR HAVING A CHANNEL WITH TENSILE STRAIN AND ORIENTED ALONG...
- Publication number 20070252144
- Publication date Nov 1, 2007
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for fabrication of a stressed MOS device
- Publication number 20070072380
- Publication date Mar 29, 2007
- Advanced Micro Devices, Inc.
- Frank Wirbeleit
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for fabricating a stressed MOS device
- Publication number 20070032024
- Publication date Feb 8, 2007
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for fabricating a stressed MOS device
- Publication number 20070026599
- Publication date Feb 1, 2007
- Advanced Micro Devices, Inc.
- Igor Peidous
- H01 - BASIC ELECTRIC ELEMENTS

IGOR V. PEIDOUS

Person

Patents Grantslast 30 patents

Integrated circuit employing variable thickness film

Methods of forming a metal silicide region in an integrated circuit

Methods to adjust threshold voltage in semiconductor devices

Method for fabricating interconnect structures for semiconductor de...

Transistor having a channel with tensile strain and oriented along...

Methods for fabricating a stressed MOS device

Stress enhanced transistor

Transistor having a channel with tensile strain and oriented along...

Methods for fabricating low contact resistance CMOS circuits

Stress enhanced transistor and methods for its fabrication

Stressed MOS device

Methods for fabricating dual material gate in a semiconductor device

Field effect transistors and methods for fabricating the same

Stress enhanced MOS transistor and methods for its fabrication

Semiconductor structures including multiple crystallographic orient...

Methods for fabricating a stressed MOS device

Stressed MOS device and methods for its fabrication

Methods for fabricating semiconductor substrates with silicon regio...

Stressed MOS device and method for its fabrication

Methods for fabricating a CMOS device including silicide contacts

Methods for fabrication of a stressed MOS device

Patents Applicationslast 30 patents

METHODS FOR FILLING HIGH ASPECT RATIO FEATURES ON SUBSTRATES

METHODS OF FORMING A METAL SILICIDE REGION IN AN INTEGRATED CIRCUIT

METHODS TO ADJUST THRESHOLD VOLTAGE IN SEMICONDUCTOR DEVICES

TRANSISTOR HAVING A CHANNEL WITH TENSILE STRAIN AND ORIENTED ALONG...

STRESS ENHANCED TRANSISTOR

METHOD FOR FABRICATING INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DE...

METHODS FOR FABRICATING DUAL MATERIAL GATE IN A SEMICONDUCTOR DEVICE

STRESSED MOS DEVICE AND METHODS FOR ITS FABRICATION

INTEGRATED CIRCUIT EMPLOYING VARIABLE THICKNESS FILM

STRESSED MOS DEVICE

METHODS FOR FABRICATING SEMICONDUCTOR SUBSTRATES WITH SILICON REGIO...

METHODS FOR FABRICATING LOW CONTACT RESISTANCE CMOS CIRCUITS

STRESS ENHANCED TRANSISTOR AND METHODS FOR ITS FABRICATION

STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION

SEMICONDUCTOR STRUCTURES INCLUDING MULTIPLE CRYSTALLOGRAPHIC ORIENT...

FIELD EFFECT TRANSISTORS AND METHODS FOR FABRICATING THE SAME

TRANSISTOR HAVING A CHANNEL WITH TENSILE STRAIN AND ORIENTED ALONG...

Methods for fabrication of a stressed MOS device

Methods for fabricating a stressed MOS device

Methods for fabricating a stressed MOS device