Ikuo J. Sanwo

Person

San Marcos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Open drain driver having enhanced immunity to I/O ground noise
- Patent number 6,472,906
- Issue date Oct 29, 2002
- Sony Corporation
- Ikuo Jimmy Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method of providing a programmable slew rate control...
- Patent number 5,977,790
- Issue date Nov 2, 1999
- Sony Corporation
- Ikuo Jimmy Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS gigabit serial link differential transmitter and receiver
- Patent number 5,977,819
- Issue date Nov 2, 1999
- NCR Corporation
- Ikuo Jimmy Sanwo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High speed test fixture
- Patent number 5,923,176
- Issue date Jul 13, 1999
- NCR Corporation
- Warren W. Porter
- G01 - MEASURING TESTING
Information Patent Grant
High speed CMOS bus transmitter and receiver
- Patent number 5,903,167
- Issue date May 11, 1999
- Sony Corporation
- Ikuo Jimmy Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS gigabit serial link differential transmitter and receiver
- Patent number 5,684,429
- Issue date Nov 4, 1997
- NCR Corporation
- Ikuo Jimmy Sanwo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low voltage CMOS to low voltage PECL converter
- Patent number 5,633,602
- Issue date May 27, 1997
- NCR Corporation
- Ikuo J. Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed memory packaging scheme
- Patent number 5,530,623
- Issue date Jun 25, 1996
- NCR Corporation
- Ikuo J. Sanwo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for containing and cooling an integrated circuit device h...
- Patent number 5,436,793
- Issue date Jul 25, 1995
- NCR Corporation
- Ikuo J. Sanwo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Containing and cooling apparatus for an integrated circuit device h...
- Patent number 5,343,360
- Issue date Aug 30, 1994
- NCR Corporation
- Ikuo J. Sanwo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Clamping circuit for data transfer bus
- Patent number 5,128,557
- Issue date Jul 7, 1992
- NCR Corporation
- Gregory H. Milby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CMOS circuit with programmable input threshold
- Patent number 5,059,835
- Issue date Oct 22, 1991
- NCR Corporation
- Donald K. Lauffer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed digital computer data transfer system having reduced bus...
- Patent number 5,030,857
- Issue date Jul 9, 1991
- NCR Corporation
- Ikuo J. Sanwo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed CMOS backpanel transceiver
- Patent number 5,019,728
- Issue date May 28, 1991
- NCR Corporation
- Ikuo J. Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed computer data transfer system
- Patent number 4,992,678
- Issue date Feb 12, 1991
- NCR Corporation
- Ikuo J. Sanwo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Temperature compensated high speed ECL-to-CMOS logic level translator
- Patent number 4,968,905
- Issue date Nov 6, 1990
- NCR Corporation
- Ikuo J. Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Stackable integrated circuit chip package with improved heat removal
- Patent number 4,953,060
- Issue date Aug 28, 1990
- NCR Corporation
- Donald K. Lauffer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Data transmission system
- Patent number 4,918,329
- Issue date Apr 17, 1990
- NCR Corporation
- Gregory H. Milby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ECL to CMOS converter
- Patent number 4,888,501
- Issue date Dec 19, 1989
- NCR Corporation
- Ikuo J. Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Three input exclusive OR-NOR gate circuit
- Patent number 4,888,499
- Issue date Dec 19, 1989
- NCR Corporation
- Ikuo J. Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Signal edge trimmer circuit
- Patent number 4,823,024
- Issue date Apr 18, 1989
- NCR Corporation
- Ikuo J. Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frostless interface supercooled VLSI system
- Patent number 4,800,422
- Issue date Jan 24, 1989
- NCR Corporation
- Ikuo J. Sanwo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High speed ECL to CMOS converter
- Patent number 4,785,205
- Issue date Nov 15, 1988
- NCR Corporation
- Ikuo J. Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
3-input Exclusive-OR gate circuit
- Patent number 4,749,887
- Issue date Jun 7, 1988
- NCR Corporation
- Ikuo J. Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cryogenic packaging scheme
- Patent number 4,734,820
- Issue date Mar 29, 1988
- NCR Corporation
- Donald K. Lauffer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Terminator for a cmos transceiver device
- Patent number 4,713,827
- Issue date Dec 15, 1987
- NCR Corporation
- Donald K. Lauffer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
CMOS to ECL converter-buffer
- Patent number 4,704,549
- Issue date Nov 3, 1987
- NCR Corporation
- Ikuo J. Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Two clock boot circuit
- Patent number 4,689,496
- Issue date Aug 25, 1987
- NCR Corporation
- William O. Kerber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Temperature compensated CMOS to ECL translator
- Patent number 4,656,375
- Issue date Apr 7, 1987
- NCR Corporation
- Donald K. Lauffer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Assist circuit for improving the rise time of an electronic signal
- Patent number 4,647,797
- Issue date Mar 3, 1987
- NCR Corporation
- Ikuo J. Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Method of improving mount assembly in a multilayer PCB's
- Publication number 20030054589
- Publication date Mar 20, 2003
- Sony Corporation
- Yoshinari Matsuda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Open drain driver having enhanced immunity to I/O ground noise
- Publication number 20020113621
- Publication date Aug 22, 2002
- Sony Corporation and Sony Electronics Inc.
- Ikuo Jimmy Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and method of providing a four input logic function
- Publication number 20020089354
- Publication date Jul 11, 2002
- Ikuo Jimmy Sanwo
- H03 - BASIC ELECTRONIC CIRCUITRY

Ikuo J. Sanwo

Person

Patents Grantslast 30 patents

Open drain driver having enhanced immunity to I/O ground noise

Apparatus and method of providing a programmable slew rate control...

CMOS gigabit serial link differential transmitter and receiver

High speed test fixture

High speed CMOS bus transmitter and receiver

CMOS gigabit serial link differential transmitter and receiver

Low voltage CMOS to low voltage PECL converter

High speed memory packaging scheme

Apparatus for containing and cooling an integrated circuit device h...

Containing and cooling apparatus for an integrated circuit device h...

Clamping circuit for data transfer bus

CMOS circuit with programmable input threshold

High speed digital computer data transfer system having reduced bus...

High speed CMOS backpanel transceiver

High speed computer data transfer system

Temperature compensated high speed ECL-to-CMOS logic level translator

Stackable integrated circuit chip package with improved heat removal

Data transmission system

ECL to CMOS converter

Three input exclusive OR-NOR gate circuit

Signal edge trimmer circuit

Frostless interface supercooled VLSI system

High speed ECL to CMOS converter

3-input Exclusive-OR gate circuit

Cryogenic packaging scheme

Terminator for a cmos transceiver device

CMOS to ECL converter-buffer

Two clock boot circuit

Temperature compensated CMOS to ECL translator

Assist circuit for improving the rise time of an electronic signal

Patents Applicationslast 30 patents

Method of improving mount assembly in a multilayer PCB's

Open drain driver having enhanced immunity to I/O ground noise

Apparatus and method of providing a four input logic function