Ilie Marian Poenaru

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Bucharest, RO

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Patents Grantslast 30 patents

Information Patent Grant
Method for reducing charge loss in analog floating gate cell
- Patent number 7,616,501
- Issue date Nov 10, 2009
- Semiconductor Components Industries, LLC
- Radu A. Sporea
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory cell in standard CMOS process
- Patent number 7,558,111
- Issue date Jul 7, 2009
- Catalyst Semiconductor, Inc.
- Sabin A. Eftimie
- G11 - INFORMATION STORAGE
Information Patent Grant
Precision non-volatile CMOS reference circuit
- Patent number 7,245,536
- Issue date Jul 17, 2007
- Catalyst Semiconductor, Inc.
- Ilie Marian I. Poenaru
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile CMOS reference circuit
- Patent number 7,149,123
- Issue date Dec 12, 2006
- Catalyst Semiconductor, Inc.
- Sorin S. Georgescu
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable analog bias circuits using floating gate CMOS technology
- Patent number 6,970,037
- Issue date Nov 29, 2005
- Catalyst Semiconductor, Inc.
- Shashi B. Sakhuja
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
Hysteresis Circuit Without Static Quiescent Current
- Publication number 20080238513
- Publication date Oct 2, 2008
- Catalyst Semiconductor, Inc.
- Ilie Marian I. Poenaru
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method For Reducing Charge Loss In Analog Floating Gate Cell
- Publication number 20080130362
- Publication date Jun 5, 2008
- Radu A. Sporea
- G11 - INFORMATION STORAGE
Information Patent Application
Non-Volatile Memory Cell In Standard CMOS Process
- Publication number 20080055965
- Publication date Mar 6, 2008
- Catalyst Semiconductor, Inc.
- Sabin A. Eftimie
- G11 - INFORMATION STORAGE
Information Patent Application
Non-volatile CMOS reference circuit
- Publication number 20050219916
- Publication date Oct 6, 2005
- Catalyst Semiconductor, Inc.
- Sorin S. Georgescu
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable analog bias circuits using floating gate cmos technology
- Publication number 20050052223
- Publication date Mar 10, 2005
- Catalyst Semiconductor, Inc.
- Shashi B. Sakhuja
- G05 - CONTROLLING REGULATING