Ilya Iosephovich Novof

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Phase locked loop having adaptive jitter reduction
- Patent number 5,828,255
- Issue date Oct 27, 1998
- International Business Machines Corporation
- Ram Kelkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay equalization apparatus and method
- Patent number 5,825,226
- Issue date Oct 20, 1998
- International Business Machines Corporation
- Frank D. Ferraiolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Computer controlled olfactory mixer and dispenser for use in multim...
- Patent number 5,724,256
- Issue date Mar 3, 1998
- International Business Machines Corporation
- Joseph Kinman Lee
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Anti-latching mechanism for phase lock loops
- Patent number 5,694,087
- Issue date Dec 2, 1997
- International Business Machines Corporation
- Frank D. Ferraiolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-lock indicator circuit with phase-only detection
- Patent number 5,680,076
- Issue date Oct 21, 1997
- International Business Machines Corporation
- Ram Kelkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit chip having built-in self measurement for PLL ji...
- Patent number 5,663,991
- Issue date Sep 2, 1997
- International Business Machines Corporation
- Ram Kelkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency-lock indicator circuit with frequency-only detection
- Patent number 5,656,977
- Issue date Aug 12, 1997
- International Business Machines Corporation
- Ram Kelkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
All FET fully integrated current reference circuit
- Patent number 5,627,456
- Issue date May 6, 1997
- International Business Machines Corporation
- Ilya I. Novof
- G05 - CONTROLLING REGULATING
Information Patent Grant
Phase locked loop circuit with phase/frequency detector which elimi...
- Patent number 5,546,052
- Issue date Aug 13, 1996
- International Business Machines Corporation
- John S. Austin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated compact capacitor-resistor/inductor configuration
- Patent number 5,541,442
- Issue date Jul 30, 1996
- International Business Machines Corporation
- Richard F. Keil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resistorless phase locked loop circuit employing direct current inj...
- Patent number 5,513,225
- Issue date Apr 30, 1996
- International Business Machines Corporation
- Ram Kelkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Charge pump circuit with symmetrical current output for phase-contr...
- Patent number 5,508,660
- Issue date Apr 16, 1996
- International Business Machines Corporation
- John E. Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differential current controlled oscillator with variable load
- Patent number 5,495,207
- Issue date Feb 27, 1996
- International Business Machines Corporation
- Ilya I. Novof
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for reducing jitter in a phase locked loop cir...
- Patent number 5,491,439
- Issue date Feb 13, 1996
- International Business Machines Corporation
- Ram Kelkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast communication link bit error rate estimator
- Patent number 5,418,789
- Issue date May 23, 1995
- International Business Machines Corporation
- John E. Gersbach
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock extraction and data regeneration logic for multiple speed dat...
- Patent number 5,371,766
- Issue date Dec 6, 1994
- International Business Machines Corporation
- John E. Gersbach
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital voltage controlled oscillator
- Patent number 5,347,234
- Issue date Sep 13, 1994
- International Business Machines Corp.
- John E. Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-level digital data regeneration system
- Patent number 5,295,155
- Issue date Mar 15, 1994
- International Business Machines Corporation
- John E. Gersbach
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Adaptive equalization and regeneration system
- Patent number 5,293,405
- Issue date Mar 8, 1994
- International Business Machines Corp.
- John E. Gersbach
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock signal latency elimination network
- Patent number 5,272,729
- Issue date Dec 21, 1993
- International Business Machines Corporation
- Roland Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase and frequency adjustable digital phase lock logic system
- Patent number 5,245,637
- Issue date Sep 14, 1993
- International Business Machines Corporation
- John E. Gersbach
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital data link performance monitor
- Patent number 5,220,581
- Issue date Jun 15, 1993
- International Business Machines Corporation
- Frank D. Ferraiolo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data edge phase sorting circuits
- Patent number 5,212,716
- Issue date May 18, 1993
- International Business Machines Corporation
- Frank D. Ferraiolo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital integrating clock extractor
- Patent number 5,185,768
- Issue date Feb 9, 1993
- International Business Machines Corporation
- Frank D. Ferraiolo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital data regeneration and deserialization circuits
- Patent number 5,101,203
- Issue date Mar 31, 1992
- International Business Machines Corporation
- John E. Gersbach
- H03 - BASIC ELECTRONIC CIRCUITRY

Ilya Iosephovich Novof

Person

Patents Grantslast 30 patents

Phase locked loop having adaptive jitter reduction

Delay equalization apparatus and method

Computer controlled olfactory mixer and dispenser for use in multim...

Anti-latching mechanism for phase lock loops

Phase-lock indicator circuit with phase-only detection

Integrated circuit chip having built-in self measurement for PLL ji...

Frequency-lock indicator circuit with frequency-only detection

All FET fully integrated current reference circuit

Phase locked loop circuit with phase/frequency detector which elimi...

Integrated compact capacitor-resistor/inductor configuration

Resistorless phase locked loop circuit employing direct current inj...

Charge pump circuit with symmetrical current output for phase-contr...

Differential current controlled oscillator with variable load

Method and apparatus for reducing jitter in a phase locked loop cir...

Fast communication link bit error rate estimator

Clock extraction and data regeneration logic for multiple speed dat...

Digital voltage controlled oscillator

Multi-level digital data regeneration system

Adaptive equalization and regeneration system

Clock signal latency elimination network

Phase and frequency adjustable digital phase lock logic system

Digital data link performance monitor

Data edge phase sorting circuits

Digital integrating clock extractor

Digital data regeneration and deserialization circuits