Ilyas Elkin

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Full adder cell with improved power efficiency
- Patent number 11,294,631
- Issue date Apr 5, 2022
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full adder cell with improved power efficiency
- Patent number 11,169,779
- Issue date Nov 9, 2021
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power flip-flop element with gated clock
- Patent number 10,931,266
- Issue date Feb 23, 2021
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Radix-4 multiplier partial product generation with improved area an...
- Patent number 10,466,968
- Issue date Nov 5, 2019
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient scan latch systems and methods
- Patent number 10,120,028
- Issue date Nov 6, 2018
- NVIDIA Corporation
- Ilyas Elkin
- G01 - MEASURING TESTING
Information Patent Grant
Latch and flip-flop circuits with shared clock-enabled supply nodes
- Patent number 9,667,230
- Issue date May 30, 2017
- NVIDIA Corporation
- Matthew Rudolph Fojtik
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Via resistance analysis systems and methods
- Patent number 9,496,853
- Issue date Nov 15, 2016
- NVIDIA Corporation
- Wojciech Jakub Poppe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Determining on-chip voltage and temperature
- Patent number 9,448,125
- Issue date Sep 20, 2016
- NVIDIA Corporation
- Abhishek Singh
- G01 - MEASURING TESTING
Information Patent Grant
Low power master-slave flip-flop
- Patent number 9,438,213
- Issue date Sep 6, 2016
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient scan latch systems and methods
- Patent number 9,435,861
- Issue date Sep 6, 2016
- NVIDIA Corporation
- Ilyas Elkin
- G01 - MEASURING TESTING
Information Patent Grant
Coupling resistance and capacitance analysis systems and methods
- Patent number 9,425,772
- Issue date Aug 23, 2016
- NVIDIA Corporation
- Wojciech Jakub Poppe
- G01 - MEASURING TESTING
Information Patent Grant
Latch circuit with a bridging device
- Patent number 9,077,329
- Issue date Jul 7, 2015
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power master-slave flip-flop
- Patent number 9,071,233
- Issue date Jun 30, 2015
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for examining asymetric operations
- Patent number 8,952,705
- Issue date Feb 10, 2015
- NVIDIA Corporation
- Ilyas Elkin
- G01 - MEASURING TESTING
Information Patent Grant
Clock gating latch, method of operation thereof and integrated circ...
- Patent number 8,890,573
- Issue date Nov 18, 2014
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Latch circuit with a bridging device
- Patent number 8,659,337
- Issue date Feb 25, 2014
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Active echo on-die repeater circuit
- Patent number 8,035,425
- Issue date Oct 11, 2011
- Oracle America, Inc.
- Robert P. Masleid
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for test of asynchronous pipelines
- Patent number 7,890,826
- Issue date Feb 15, 2011
- Oracle America, Inc.
- Ishwardutt Parulkar
- G01 - MEASURING TESTING
Information Patent Grant
Low-power semi-dynamic flip-flop with smart keeper
- Patent number 7,629,815
- Issue date Dec 8, 2009
- Sun Microsystems, Inc.
- Bo Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
One gate delay output noise insensitive latch
- Patent number 7,164,302
- Issue date Jan 16, 2007
- Sun Microsystems, Inc.
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DATA PATH CIRCUIT DESIGN USING REINFORCEMENT LEARNING
- Publication number 20230139623
- Publication date May 4, 2023
- NVIDIA Corporation
- Rajarshi Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIORITY ENCODER-BASED TECHNIQUES FOR COMPUTING THE MINIMUM OR THE...
- Publication number 20230100785
- Publication date Mar 30, 2023
- NVIDIA Corporation
- Ilyas ELKIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY
- Publication number 20210124558
- Publication date Apr 29, 2021
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY
- Publication number 20210124559
- Publication date Apr 29, 2021
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT SCAN LATCH SYSTEMS AND METHODS
- Publication number 20170234927
- Publication date Aug 17, 2017
- NVIDIA Corporation
- Ilyas Elkin
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER FLIP-FLOP ELEMENT WITH GATED CLOCK
- Publication number 20160043706
- Publication date Feb 11, 2016
- NVIDIA Corporation
- Ilyas ELKIN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER MASTER-SLAVE FLIP-FLOP
- Publication number 20150263708
- Publication date Sep 17, 2015
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER MASTER-SLAVE FLIP-FLOP
- Publication number 20150028927
- Publication date Jan 29, 2015
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LATCH CIRCUIT WITH A BRIDGING DEVICE
- Publication number 20140125393
- Publication date May 8, 2014
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EFFICIENT SCAN LATCH SYSTEMS AND METHODS
- Publication number 20140122949
- Publication date May 1, 2014
- NVIDIA Corporation
- Ilyas Elkin
- G01 - MEASURING TESTING
Information Patent Application
CLOCK GATING LATCH, METHOD OF OPERATION THEREOF AND INTEGRATED CIRC...
- Publication number 20140070847
- Publication date Mar 13, 2014
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD FOR EXAMINING ASYMETRIC OPERATIONS
- Publication number 20130106438
- Publication date May 2, 2013
- NVIDIA Corporation
- Ilyas Elkin
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR EXAMINING LEAKAGE IMPACTS
- Publication number 20130106524
- Publication date May 2, 2013
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DETERMINING ON-CHIP VOLTAGE AND TEMPERATURE
- Publication number 20130110437
- Publication date May 2, 2013
- NVIDIA Corporation
- Abhishek Singh
- G01 - MEASURING TESTING
Information Patent Application
COUPLING RESISTANCE AND CAPACITANCE ANALYSIS SYSTEMS AND METHODS
- Publication number 20130027140
- Publication date Jan 31, 2013
- NVIDIA Corporation
- Wojciech Jakub Poppe
- G01 - MEASURING TESTING
Information Patent Application
LATCH CIRCUIT WITH A BRIDGING DEVICE
- Publication number 20130021078
- Publication date Jan 24, 2013
- Ilyas ELKIN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
VIA RESISTANCE ANALYSIS SYSTEMS AND METHODS
- Publication number 20130021107
- Publication date Jan 24, 2013
- NVIDIA Corporation
- Wojciech Jakub Poppe
- G01 - MEASURING TESTING
Information Patent Application
ACTIVE ECHO ON-DIE REPEATER CIRCUIT
- Publication number 20100164557
- Publication date Jul 1, 2010
- Robert P. Masleid
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for test of asynchronous pipelines
- Publication number 20080141088
- Publication date Jun 12, 2008
- Sun Microsystems, Inc.
- Ishwardutt Parulkar
- G01 - MEASURING TESTING

Ilyas Elkin

Person

Patents Grantslast 30 patents

Full adder cell with improved power efficiency

Full adder cell with improved power efficiency

Low power flip-flop element with gated clock

Radix-4 multiplier partial product generation with improved area an...

Efficient scan latch systems and methods

Latch and flip-flop circuits with shared clock-enabled supply nodes

Via resistance analysis systems and methods

Determining on-chip voltage and temperature

Low power master-slave flip-flop

Efficient scan latch systems and methods

Coupling resistance and capacitance analysis systems and methods

Latch circuit with a bridging device

Low power master-slave flip-flop

System and method for examining asymetric operations

Clock gating latch, method of operation thereof and integrated circ...

Latch circuit with a bridging device

Active echo on-die repeater circuit

Method and apparatus for test of asynchronous pipelines

Low-power semi-dynamic flip-flop with smart keeper

One gate delay output noise insensitive latch

Patents Applicationslast 30 patents

DATA PATH CIRCUIT DESIGN USING REINFORCEMENT LEARNING

PRIORITY ENCODER-BASED TECHNIQUES FOR COMPUTING THE MINIMUM OR THE...

FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY

FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY

EFFICIENT SCAN LATCH SYSTEMS AND METHODS

LOW POWER FLIP-FLOP ELEMENT WITH GATED CLOCK

LOW POWER MASTER-SLAVE FLIP-FLOP

LOW POWER MASTER-SLAVE FLIP-FLOP

LATCH CIRCUIT WITH A BRIDGING DEVICE

EFFICIENT SCAN LATCH SYSTEMS AND METHODS

CLOCK GATING LATCH, METHOD OF OPERATION THEREOF AND INTEGRATED CIRC...

SYSTEM AND METHOD FOR EXAMINING ASYMETRIC OPERATIONS

SYSTEM AND METHOD FOR EXAMINING LEAKAGE IMPACTS

DETERMINING ON-CHIP VOLTAGE AND TEMPERATURE

COUPLING RESISTANCE AND CAPACITANCE ANALYSIS SYSTEMS AND METHODS

LATCH CIRCUIT WITH A BRIDGING DEVICE

VIA RESISTANCE ANALYSIS SYSTEMS AND METHODS

ACTIVE ECHO ON-DIE REPEATER CIRCUIT

Method and apparatus for test of asynchronous pipelines